Abstract: There are provided a plurality of standard cell blocks (2) within an IC chip (1), and an aluminium wiring layer is formed in an aluminium wiring region (8) provided between the standard cell blocks (2) to electrically connect the standard cell blocks (2) to each other. An n-type epitaxial region (4), a p-type diffusion region (5) and an n-type diffusion region (6) are incorporated in an underlayer of the aluminium wiring region (8), to thereby form an evaluation device which is an npn bipolar transistor under the aluminium wiring region (8). A semiconductor device which is capable of accurately evaluating its finished product by the inspection of the evaluation device is provided without the damage of an integration level.