Patents by Inventor Takuo Ohashi
Takuo Ohashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11195744Abstract: A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.Type: GrantFiled: February 22, 2019Date of Patent: December 7, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Motoki Fujii, Takuo Ohashi, Daisuke Nishida
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Patent number: 10593696Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.Type: GrantFiled: May 10, 2019Date of Patent: March 17, 2020Assignee: Toshiba Memory CorporationInventors: Kazuharu Yamabe, Ryota Suzuki, Tatsuo Izumi, Masahiro Fukuda, Takuo Ohashi
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Publication number: 20200075391Abstract: A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.Type: ApplicationFiled: February 22, 2019Publication date: March 5, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Motoki FUJII, Takuo OHASHI, Daisuke NISHIDA
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Publication number: 20190273093Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.Type: ApplicationFiled: May 10, 2019Publication date: September 5, 2019Applicant: Toshiba Memory CorporationInventors: Kazuharu YAMABE, Ryota Suzuki, Tatsuo Izumi, Masahiro Fukuda, Takuo Ohashi
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Patent number: 10332904Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.Type: GrantFiled: March 13, 2017Date of Patent: June 25, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuharu Yamabe, Ryota Suzuki, Tatsuo Izumi, Masahiro Fukuda, Takuo Ohashi
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Patent number: 10283517Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.Type: GrantFiled: September 13, 2017Date of Patent: May 7, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takuo Ohashi, Fumiki Aiso
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Patent number: 10186521Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending through the stacked body in a stacking direction of the stacked body, and a charge storage portion provided between the semiconductor body and the electrode layers. The semiconductor body includes a first semiconductor film, and a second semiconductor film provided between the first semiconductor film and the charge storage portion. An average grain size of a crystal of the second semiconductor film is larger than an average grain size of a crystal of the first semiconductor film.Type: GrantFiled: March 15, 2017Date of Patent: January 22, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Atsushi Fukumoto, Fumiki Aiso, Hajime Nagano, Takuo Ohashi
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Patent number: 9960174Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; an electrode layer; a first insulating film; a charge storage film; and a second insulating film. The first insulating film is provided between the electrode layer and the semiconductor layer. The charge storage film is provided between the first insulating film and the electrode layer. The charge storage film includes a charge trapping layer and a floating electrode layer. The floating electrode layer includes doped silicon. The second insulating film is provided between the floating electrode layer and the electrode layer.Type: GrantFiled: March 7, 2016Date of Patent: May 1, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takuo Ohashi, Masaaki Higuchi
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Publication number: 20180083027Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.Type: ApplicationFiled: March 13, 2017Publication date: March 22, 2018Applicant: Toshiba Memory CorporationInventors: Kazuharu YAMABE, Ryota SUZUKI, Tatsuo IZUMI, Masahiro FUKUDA, Takuo OHASHI
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Publication number: 20180083028Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending through the stacked body in a stacking direction of the stacked body, and a charge storage portion provided between the semiconductor body and the electrode layers. The semiconductor body includes a first semiconductor film, and a second semiconductor film provided between the first semiconductor film and the charge storage portion. An average grain size of a crystal of the second semiconductor film is larger than an average grain size of a crystal of the first semiconductor film.Type: ApplicationFiled: March 15, 2017Publication date: March 22, 2018Applicant: Toshiba Memory CorporationInventors: Atsushi FUKUMOTO, Fumiki AISO, Hajime NAGANO, Takuo OHASHI
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Publication number: 20180006053Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.Type: ApplicationFiled: September 13, 2017Publication date: January 4, 2018Applicant: Toshiba Memory CorporationInventors: Takuo OHASHI, Fumiki AISO
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Patent number: 9793290Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.Type: GrantFiled: March 16, 2016Date of Patent: October 17, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takuo Ohashi, Fumiki Aiso
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Patent number: 9754954Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: GrantFiled: July 5, 2016Date of Patent: September 5, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaaki Higuchi, Katsuyuki Sekine, Fumiki Aiso, Takuo Ohashi, Tatsuya Okamoto
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Publication number: 20170069647Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; an electrode layer; a first insulating film; a charge storage film; and a second insulating film. The first insulating film is provided between the electrode layer and the semiconductor layer. The charge storage film is provided between the first insulating film and the electrode layer. The charge storage film includes a charge trapping layer and a floating electrode layer. The floating electrode layer includes doped silicon. The second insulating film is provided between the floating electrode layer and the electrode layer.Type: ApplicationFiled: March 7, 2016Publication date: March 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takuo OHASHI, Masaaki HIGUCHI
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Publication number: 20170018569Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.Type: ApplicationFiled: March 16, 2016Publication date: January 19, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takuo OHASHI, Fumiki AISO
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Publication number: 20160315092Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: ApplicationFiled: July 5, 2016Publication date: October 27, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Fumiki AISO, Takuo OHASHI, Tatsuya OKAMOTO
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Patent number: 9406691Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: GrantFiled: September 24, 2015Date of Patent: August 2, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Higuchi, Katsuyuki Sekine, Fumiki Aiso, Takuo Ohashi, Tatsuya Okamoto
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Publication number: 20160013201Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: ApplicationFiled: September 24, 2015Publication date: January 14, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Fumiki AISO, Takuo OHASHI, Tatsuya OKAMOTO
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Patent number: 9166032Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: GrantFiled: September 11, 2014Date of Patent: October 20, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Higuchi, Katsuyuki Sekine, Fumiki Aiso, Takuo Ohashi, Tatsuya Okamoto
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Patent number: 9027588Abstract: A pressure control device according to an embodiment includes a solenoid portion for regulating a gate opening of a valve through a first shaft portion connected to the valve, a micrometer for regulating the gate opening through the first shaft portion and a second shaft portion having an axial direction which is parallel with that of the first shaft portion when the second shaft portion is connected to the first shaft portion, and a switching portion. The switching portion switches to cause the solenoid portion to regulate the gate opening or to cause the micrometer to regulate the gate opening.Type: GrantFiled: April 24, 2012Date of Patent: May 12, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Mari Kusunoki, Takuo Ohashi, Shinji Miyazaki, Norihiko Kamiura