Abstract: A neutral-point-clamped PWM inverter arrangement for reducing output harmonic content. The arrangement includes a DC power source circuit having positive, negative and neutral terminals, a first group of switching elements connected at one end to the power source positive terminal, a second group of switching elements connected at one end to the power source negative terminal and at the other end to the corresponding switching elements of the first group, respectively, a third group of switching elements connected between the power source neutral terminal and the junctions of the switching elements of the first group and the second group, and a fourth group of switching elements connected in parallel with corresponding switching elements of the third group, respectively. Output terminals are connected to points where a switching element of the first group is connected to the corresponding ones of the second group to provide phase output voltages.

Abstract: An apparatus for controlling an inverter main circuit has a memory circuit for storing digital control signals which correspond to 180.degree./n portions of output voltage waveforms of the inverter main circuit, where n is an integer. The memory circuit has a plurality of memory areas. One of the memory areas is designated by a digital signal supplied from a speed setting circuit. And the addresses of any memory area thus designated are designated by output signals of an up-down counter, one after another in ascending order of their serial numbers (forward direction) and in descending order of their serial numbers (backward direction). As they are designated, the memory regions corresponding to addresses supplies control signals. Every time the addressing direction is changed, the up-down counter generates a clock signal to a converter circuit which has 2n output terminals.