Patents by Inventor Takuro Homma

Takuro Homma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9583502
    Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: February 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Nishikizawa, Takuro Homma, Hiraku Chakihara, Mitsuhiro Noguchi
  • Patent number: 9536821
    Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 3, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Homma, Katsuhiko Hotta, Takashi Moriyama
  • Publication number: 20160027794
    Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.
    Type: Application
    Filed: October 2, 2015
    Publication date: January 28, 2016
    Inventors: Hiroshi Nishikizawa, Takuro Homma, Hiraku Chakihara, Mitsuhiro Noguchi
  • Patent number: 9171727
    Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: October 27, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Nishikizawa, Takuro Homma, Hiraku Chakihara, Mitsuhiro Noguchi
  • Publication number: 20150194381
    Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.
    Type: Application
    Filed: March 24, 2015
    Publication date: July 9, 2015
    Inventors: Takuro HOMMA, Katsuhiko HOTTA, Takashi MORIYAMA
  • Patent number: 9048200
    Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: June 2, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Homma, Katsuhiko Hotta, Takashi Moriyama
  • Publication number: 20140242767
    Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.
    Type: Application
    Filed: January 2, 2014
    Publication date: August 28, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: HIROSHI NISHIKIZAWA, TAKURO HOMMA, HIRAKU CHAKIHARA, MITSUHIRO NOGUCHI
  • Patent number: 8513808
    Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Takeshi Furusawa, Toshikazu Matsui, Takuro Homma
  • Patent number: 8461642
    Abstract: The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.
    Type: Grant
    Filed: August 2, 2009
    Date of Patent: June 11, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Homma, Yasushi Ishii, Kota Funayama
  • Publication number: 20130065330
    Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 14, 2013
    Inventors: TAKURO HOMMA, Katsuhiko Hotta, Takashi Moriyama
  • Patent number: 8390134
    Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: March 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Homma, Yoshifumi Takata
  • Patent number: 8373270
    Abstract: In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and high humidity (such as about 80% RH). For that test, the inventors of the present invention found the phenomenon of occurrence of separation of titanium nitride film as the anti-reflection film from upper film and of generation of cracks in the titanium nitride film at an edge part of upper surface of the aluminum-based bonding pad applied with a positive voltage during the high-temperature and high-humidity test caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Homma, Katsuhiko Hotta, Takashi Moriyama
  • Publication number: 20110266679
    Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 3, 2011
    Inventors: Katsuhiko Hotta, Takeshi Furusawa, Toshikazu Matsui, Takuro Homma
  • Publication number: 20100295044
    Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 25, 2010
    Inventors: Takuro HOMMA, Yoshifumi Takata
  • Publication number: 20100264414
    Abstract: In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and high humidity (such as about 80% RH). For that test, the inventors of the present invention found the phenomenon of occurrence of separation of titanium nitride film as the anti-reflection film from upper film and of generation of cracks in the titanium nitride film at an edge part of upper surface of the aluminum-based bonding pad applied with a positive voltage during the high-temperature and high-humidity test caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film.
    Type: Application
    Filed: April 15, 2010
    Publication date: October 21, 2010
    Inventors: Takuro HOMMA, Katsuhiko Hotta, Takashi Moriyama
  • Publication number: 20100059810
    Abstract: The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.
    Type: Application
    Filed: August 2, 2009
    Publication date: March 11, 2010
    Inventors: Takuro HOMMA, Yasushi Ishii, Kota Funayama
  • Patent number: 5733458
    Abstract: The interface between two nonmagnetic fluids, typically liquid layers, in contact with each other is changed by applying a magnetic field thereto. The interface is raised or depressed into an upward or downward convex shape.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: March 31, 1998
    Assignee: TDK Corporation
    Inventors: Koichi Kitazawa, Hiroharu Sugawara, Noriyuki Hirota, Takuro Homma, Satoshi Maruyama, Shinichi Yamashita, Jun Nakagawa