Patents by Inventor Takuro Homma
Takuro Homma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9583502Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.Type: GrantFiled: October 2, 2015Date of Patent: February 28, 2017Assignee: Renesas Electronics CorporationInventors: Hiroshi Nishikizawa, Takuro Homma, Hiraku Chakihara, Mitsuhiro Noguchi
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Patent number: 9536821Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.Type: GrantFiled: March 24, 2015Date of Patent: January 3, 2017Assignee: Renesas Electronics CorporationInventors: Takuro Homma, Katsuhiko Hotta, Takashi Moriyama
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Publication number: 20160027794Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.Type: ApplicationFiled: October 2, 2015Publication date: January 28, 2016Inventors: Hiroshi Nishikizawa, Takuro Homma, Hiraku Chakihara, Mitsuhiro Noguchi
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Patent number: 9171727Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.Type: GrantFiled: January 2, 2014Date of Patent: October 27, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Nishikizawa, Takuro Homma, Hiraku Chakihara, Mitsuhiro Noguchi
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Publication number: 20150194381Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.Type: ApplicationFiled: March 24, 2015Publication date: July 9, 2015Inventors: Takuro HOMMA, Katsuhiko HOTTA, Takashi MORIYAMA
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Patent number: 9048200Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.Type: GrantFiled: September 11, 2012Date of Patent: June 2, 2015Assignee: Renesas Electronics CorporationInventors: Takuro Homma, Katsuhiko Hotta, Takashi Moriyama
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Publication number: 20140242767Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.Type: ApplicationFiled: January 2, 2014Publication date: August 28, 2014Applicant: Renesas Electronics CorporationInventors: HIROSHI NISHIKIZAWA, TAKURO HOMMA, HIRAKU CHAKIHARA, MITSUHIRO NOGUCHI
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Patent number: 8513808Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.Type: GrantFiled: April 27, 2011Date of Patent: August 20, 2013Assignee: Renesas Electronics CorporationInventors: Katsuhiko Hotta, Takeshi Furusawa, Toshikazu Matsui, Takuro Homma
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Patent number: 8461642Abstract: The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.Type: GrantFiled: August 2, 2009Date of Patent: June 11, 2013Assignee: Renesas Electronics CorporationInventors: Takuro Homma, Yasushi Ishii, Kota Funayama
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Publication number: 20130065330Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.Type: ApplicationFiled: September 11, 2012Publication date: March 14, 2013Inventors: TAKURO HOMMA, Katsuhiko Hotta, Takashi Moriyama
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Patent number: 8390134Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.Type: GrantFiled: May 19, 2010Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Takuro Homma, Yoshifumi Takata
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Patent number: 8373270Abstract: In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and high humidity (such as about 80% RH). For that test, the inventors of the present invention found the phenomenon of occurrence of separation of titanium nitride film as the anti-reflection film from upper film and of generation of cracks in the titanium nitride film at an edge part of upper surface of the aluminum-based bonding pad applied with a positive voltage during the high-temperature and high-humidity test caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film.Type: GrantFiled: April 15, 2010Date of Patent: February 12, 2013Assignee: Renesas Electronics CorporationInventors: Takuro Homma, Katsuhiko Hotta, Takashi Moriyama
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Publication number: 20110266679Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.Type: ApplicationFiled: April 27, 2011Publication date: November 3, 2011Inventors: Katsuhiko Hotta, Takeshi Furusawa, Toshikazu Matsui, Takuro Homma
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Publication number: 20100295044Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.Type: ApplicationFiled: May 19, 2010Publication date: November 25, 2010Inventors: Takuro HOMMA, Yoshifumi Takata
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Publication number: 20100264414Abstract: In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and high humidity (such as about 80% RH). For that test, the inventors of the present invention found the phenomenon of occurrence of separation of titanium nitride film as the anti-reflection film from upper film and of generation of cracks in the titanium nitride film at an edge part of upper surface of the aluminum-based bonding pad applied with a positive voltage during the high-temperature and high-humidity test caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film.Type: ApplicationFiled: April 15, 2010Publication date: October 21, 2010Inventors: Takuro HOMMA, Katsuhiko Hotta, Takashi Moriyama
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Publication number: 20100059810Abstract: The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.Type: ApplicationFiled: August 2, 2009Publication date: March 11, 2010Inventors: Takuro HOMMA, Yasushi Ishii, Kota Funayama
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Patent number: 5733458Abstract: The interface between two nonmagnetic fluids, typically liquid layers, in contact with each other is changed by applying a magnetic field thereto. The interface is raised or depressed into an upward or downward convex shape.Type: GrantFiled: March 22, 1996Date of Patent: March 31, 1998Assignee: TDK CorporationInventors: Koichi Kitazawa, Hiroharu Sugawara, Noriyuki Hirota, Takuro Homma, Satoshi Maruyama, Shinichi Yamashita, Jun Nakagawa