Patents by Inventor Takuro KANEMURA

Takuro KANEMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11922690
    Abstract: A data processing system, a data processing device, and a data processing method are provided. The data processing system includes a wearable device including a display means and an imaging means and a database that is connected to the wearable device through a network. The database includes at least one of pieces of information on a cooking recipe, a cooking method, and a material. The wearable device detects a first material by the imaging means. The wearable device collects information on the first material from the database. When the first material exists in a specific region in an imaging range of the imaging means, the information on the first material is displayed on the display means. When the first material does not exist in the specific region, the information on the first material is not displayed on the display means.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro Kanemura, Taisuke Higashi, Hiroya Hibino, Atsuya Tokinosu, Hiromichi Godo, Satoru Okamoto
  • Publication number: 20230353163
    Abstract: A novel semiconductor device is provided. An analog signal is converted into a digital signal using a comparison portion comparing two current values, a control portion, and a current output digital-analog conversion portion. The control portion has a function of generating a sign bit showing a magnitude relation between the two current values, a function of converting a difference between the two current values into a digital signal by successive approximation, and a function of outputting the sign bit and the digital signal.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 2, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro KANEMURA, Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20230326491
    Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell.
    Type: Application
    Filed: May 6, 2021
    Publication date: October 12, 2023
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takuro KANEMURA, Tatsunori INOUE
  • Publication number: 20230284429
    Abstract: Provided is a semiconductor device having a novel structure. A first transistor, a second transistor, a third transistor, and a capacitor are included. The first transistor has a function of retaining a first potential corresponding to first data supplied to a gate of the third transistor through the first transistor when being in an off state. The capacitor has a function of changing the first potential retained in the gate of the third transistor into a second potential in accordance with a change in potential corresponding to second data supplied to one electrode of the capacitor. The second transistor has a function of setting a potential of one of a source and a drain of the third transistor to a potential corresponding to a potential of a gate of the second transistor. The third transistor has a function of supplying output current corresponding to a potential of the gate of the third transistor to the other of the source and the drain of the third transistor.
    Type: Application
    Filed: July 19, 2021
    Publication date: September 7, 2023
    Inventors: Hiromichi GODO, Kazuki TSUDA, Yoshiyuki KUROKAWA, Satoru OHSHITA, Takuro KANEMURA, Hidefumi RIKIMARU
  • Publication number: 20230273637
    Abstract: A control circuit of a secondary battery with a novel structure is provided. The control circuit of a secondary battery includes a first transistor, a first voltage generation circuit generating a first voltage, and a second voltage generation circuit generating a second voltage. The first voltage generation circuit includes a second transistor and a first capacitor. The second voltage generation circuit includes a third transistor and a second capacitor. The difference between the first voltage and the second voltage is set in accordance with the threshold voltage of the first transistor. When the first transistor includes a back gate, a voltage retention circuit having a function of retaining the voltage of the back gate is included. The voltage retention circuit includes a fourth transistor and a third capacitor. The third capacitor includes a ferroelectric layer between a pair of electrodes.
    Type: Application
    Filed: August 25, 2021
    Publication date: August 31, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki KUROKAWA, Kazuki TSUDA, Hiromichi GODO, Satoru OHSHITA, Takuro KANEMURA, Hidefumi RIKIMARU, Takayuki IKEDA, Yuto YAKUBO, Shunpei YAMAZAKI
  • Publication number: 20230132059
    Abstract: A semiconductor device capable of performing product-sum operation with high layout flexibility is provided. In the semiconductor device, a first layer, a second layer, and a third layer are formed in this order. The first layer includes a first cell, a first circuit, a first wiring, and a second wiring adjacent to the first wiring. The second layer includes a third wiring and a fourth wiring adjacent to the third wiring. The third layer includes an electrode and a sensor. The first circuit includes a switch. The sensor is electrically connected to the third wiring through the electrode and a first plug, a first terminal of the switch is electrically connected to the third wiring through a second plug, and a second terminal of the switch is electrically connected to the first cell through the first wiring. The electrode includes a region overlapping with the sensor and a region overlapping with the first plug.
    Type: Application
    Filed: April 5, 2021
    Publication date: April 27, 2023
    Inventors: Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takeshi AOKI, Takuro KANEMURA
  • Publication number: 20230082313
    Abstract: A semiconductor device with reduced power consumption that can perform a product-sum operation is provided. The semiconductor device includes first and second circuits, and the second circuit includes first and second switches, a current/voltage converter circuit, and a first transistor. The first circuit is electrically connected to a first terminal of the second circuit; a first terminal of the first switch is electrically connected to the first terminal of the second circuit; a second terminal of the first switch is electrically connected to an input terminal of the current/voltage converter circuit; an output terminal of the current/voltage converter circuit is electrically connected to a first terminal of the first transistor; a second terminal of the first transistor is electrically connected to a first terminal of the second switch; and a second terminal of the second switch is electrically connected to a second terminal of the second circuit.
    Type: Application
    Filed: February 12, 2021
    Publication date: March 16, 2023
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takuro KANEMURA
  • Publication number: 20230049977
    Abstract: A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell.
    Type: Application
    Filed: December 14, 2020
    Publication date: February 16, 2023
    Inventors: Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takeshi AOKI, Takuro KANEMURA
  • Publication number: 20230043910
    Abstract: A semiconductor device that has low power consumption and is capable of performing a product-sum operation is provided. The semiconductor device includes first and second cells, a first circuit, and first to third wirings. Each of the first and second cells includes a capacitor, and a first terminal of each of the capacitors is electrically connected to the third wiring. Each of the first and second cells has a function of feeding a current based on a potential held at a second terminal of the capacitor, to a corresponding one of the first and second wirings. The first circuit is electrically connected to the first and second wirings and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wiring changes and accordingly the amount of current of the first wiring changes from I1 to I3 and the amount of current of the second wiring changes from I2 to I4, the first circuit generates a current with an amount I1-I2-I3+I4.
    Type: Application
    Filed: January 8, 2021
    Publication date: February 9, 2023
    Inventors: Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takeshi AOKI, Takuro KANEMURA
  • Publication number: 20220406849
    Abstract: An imaging device having a color imaging function and an infrared imaging function is provided. The imaging device has a structure in which a first photoelectric conversion device and a second photoelectric conversion device are stacked, and the second photoelectric conversion device generates electric charge by absorbing infrared light and transmits light having a wavelength of a higher energy than that of infrared light. The first photoelectric conversion device is positioned to overlap with the second photoelectric conversion device, and generates electric charge by absorbing light (visible light) passing through the second photoelectric conversion device. Thus, a subpixel for color imaging and a subpixel for infrared imaging can be positioned to overlap with each other, and an infrared imaging function can be added without a decrease in the definition of color imaging.
    Type: Application
    Filed: November 11, 2020
    Publication date: December 22, 2022
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro Kanemura, Yusuke NEGORO
  • Publication number: 20220374203
    Abstract: A semiconductor device that inhibits signal delay and can perform parallel product-sum operations is provided. The semiconductor device includes first to fourth registers, an adder, a multiplier, a selector, and a first memory unit. An output terminal of the first register is electrically connected to an input terminal of the second register, and an output terminal of the second register is electrically connected to a first input terminal of the multiplier. An output terminal of the multiplier is electrically connected to a first input terminal of the adder, and an output terminal of the adder is electrically connected to an input terminal of the third register. An output terminal of the third register is electrically connected to a first input terminal of the selector, and an output terminal of the selector is electrically connected to an input terminal of the fourth register, and the first memory unit is electrically connected to a second input terminal of the multiplier.
    Type: Application
    Filed: October 15, 2020
    Publication date: November 24, 2022
    Inventors: Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takeshi AOKI, Takuro KANEMURA
  • Publication number: 20220351509
    Abstract: A data processing system, a data processing device, and a data processing method are provided. The data processing system includes a wearable device including a display means and an imaging means and a database that is connected to the wearable device through a network. The database includes at least one of pieces of information on a cooking recipe, a cooking method, and a material. The wearable device detects a first material by the imaging means. The wearable device collects information on the first material from the database. When the first material exists in a specific region in an imaging range of the imaging means, the information on the first material is displayed on the display means. When the first material does not exist in the specific region, the information on the first material is not displayed on the display means.
    Type: Application
    Filed: June 12, 2020
    Publication date: November 3, 2022
    Inventors: Takuro KANEMURA, Taisuke HIGASHI, Hiroya HIBINO, Atsuya TOKINOSU, Hiromichi GODO, Satoru OKAMOTO
  • Publication number: 20220276834
    Abstract: A semiconductor device which can efficiently perform reading of a weight coefficient and a product-sum operation is provided. The semiconductor device includes a product-sum operation circuit and a memory device. The product-sum operation circuit is formed using transistors formed on a semiconductor substrate, and a memory cell of the memory device is formed using an OS transistor provided to be stacked above the semiconductor substrate. The semiconductor device includes a plurality of product-sum operation units where the product-sum operation circuit and the memory cell of the memory device are electrically connected to each other. In each of the product-sum operation units, a weight coefficient stored in the memory cell can be read and a product-sum operation can be performed.
    Type: Application
    Filed: June 29, 2020
    Publication date: September 1, 2022
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takuro KANEMURA