Abstract: A storage system includes: a first storage control device; and a second storage control device, wherein, when receiving a switching instruction to switch a device in charge that controls the I/O processing for the logical storage area from the first storage control device to the second storage control device, the first storage control device performs first switching processing of notifying the second storage control device of a management device number that indicates the first storage control device as a device that manages the cache, and executing response processing to switch the device in charge, and when receiving a determination request as to whether data requested to be read from the logical storage area by a readout request hits the cache, the first storage control device determines whether the data hits the cache, and the second storage control device transmits the determination request to the first storage control device.

Abstract: A storage control device includes: an auxiliary cache memory that is a nonvolatile memory; a volatile memory; and a processor configured to execute a saving control process after a predetermined failure occurs, the saving control process being configured to (a) cause a writing control process to stop writing of data stored in the auxiliary cache memory to the storage medium, (b) secure, in the auxiliary cache memory, a storage region for storing the management information of the volatile memory, (c) generate a copy of management information of the volatile memory in the storage region, and (d) cause the writing control process to execute control to write first data stored in the volatile memory to the auxiliary cache memory or the storage medium based on the management information of the auxiliary cache memory.

Abstract: A storage control device includes: an auxiliary cache memory that is a nonvolatile memory; a volatile memory; and a processor configured to execute a saving control process after a predetermined failure occurs, the saving control process being configured to (a) cause a writing control process to stop writing of data stored in the auxiliary cache memory to the storage medium, (b) secure, in the auxiliary cache memory, a storage region for storing the management information of the volatile memory, (c) generate a copy of management information of the volatile memory in the storage region, and (d) cause the writing control process to execute control to write first data stored in the volatile memory to the auxiliary cache memory or the storage medium based on the management information of the auxiliary cache memory.

Abstract: A storage control device includes a processor configured to receive access information indicating a start position and an end position of an access area in a first volume. The processor is configured to determine, based on one or more pieces of the received access information, whether a number of blocks in a cache area is reduced as a whole by changing a position of data in the first volume. The blocks are used in response to an access to the access area and correspond to one or more unit areas in the first volume. The one or more unit areas include the access area. The processor is configured to change the position of the data in the first volume upon determining that the number of the blocks in the cache area is reduced as a whole by changing the position of the data in the first volume.

Abstract: A memory includes a plurality of pages used as a cache area. A processor allocates a first storage resource to a first link indicating a first page group of the plurality of pages, and a second storage resource to a second link indicating a second page group of the plurality of pages. The processor uses the first and the second links, and processes access requests for accessing to the first and the second storage resources, in parallel.

Abstract: A storage control device includes a processor configured to receive from a host device a write request for writing data into a memory device. The processor is configured to try to write the data into a cache memory. The processor is configured to select an operation mode of a write process for the write request from among a first mode and a second mode on the basis of whether a cache hit or a cache miss occurs at the trial. The processor is configured to return a response to the host device upon completion of writing the data into the cache memory without waiting for completion of the write process when the write process is performed in the first mode. The processor is configured to return a response to the host device upon completion of the write process when the write process is performed in the second mode.

Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.

Abstract: A memory includes a plurality of pages used as a cache area. A processor allocates a first storage resource to a first link indicating a first page group of the plurality of pages, and a second storage resource to a second link indicating a second page group of the plurality of pages. The processor uses the first and the second links, and processes access requests for accessing to the first and the second storage resources, in parallel.

Abstract: A storage control device includes a processor configured to receive access information indicating a start position and an end position of an access area in a first volume. The processor is configured to determine, based on one or more pieces of the received access information, whether a number of blocks in a cache area is reduced as a whole by changing a position of data in the first volume. The blocks are used in response to an access to the access area and correspond to one or more unit areas in the first volume. The one or more unit areas include the access area. The processor is configured to change the position of the data in the first volume upon determining that the number of the blocks in the cache area is reduced as a whole by changing the position of the data in the first volume.

Abstract: A storage control device includes a processor configured to receive from a host device a write request for writing data into a memory device. The processor is configured to try to write the data into a cache memory. The processor is configured to select an operation mode of a write process for the write request from among a first mode and a second mode on the basis of whether a cache hit or a cache miss occurs at the trial. The processor is configured to return a response to the host device upon completion of writing the data into the cache memory without waiting for completion of the write process when the write process is performed in the first mode. The processor is configured to return a response to the host device upon completion of the write process when the write process is performed in the second mode.

Abstract: A control device includes a processor. The processor is configured to collect plural types of performance information regarding a first data unit. The processor is configured to determine, on basis of the collected plural types of performance information, whether to transfer the first data unit from a first storage device which is under control of a first controller to a second storage device which is positioned as higher than the first storage device. The processor is configured to transfer the first data unit from the first storage device to the second storage device depending on a result of the determination.

Abstract: A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and performs LRU control with the use of the shared queue. The control unit also provides a local queue in the memory space of the shared cache memory. The control unit enqueues a CBE (management information) for a cache page used by a core in a process to the local queue. The control unit dequeues a plurality of CBEs from the local queue upon satisfaction of a predetermined condition, and enqueues the dequeued CBEs to the shared queue.

Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.

Abstract: A storage control device is one of a plurality of control devices each controlling different storage areas. The storage control device includes a memory and a processor coupled to the memory. The processor is configured to acquire an allocation request for allocating a storage area to a first virtual volume. The processor is configured to allocate a first storage area to the first virtual volume upon acquiring the allocation request. The first storage area is controlled by a first control device among the plurality of control devices. The first control device controls the first virtual volume.

Abstract: An apparatus includes a first cache memory, a second cache memory, and a processor coupled to the first cache memory and the second cache memory, and configured to store data in the second cache memory, the data being deleted from the first cache memory, store first data stored in a first address of the storage device, in the second cache memory, in case where the first address is included in first management information and is not included in second management information, according to a request for access to the first address of the storage device, the first management information including an address in the storage device of specific data stored in the storage device, and the second management information including an address in the storage device of data stored in both of the second cache memory and the storage device, and register the first address in the second management information.

Abstract: A control device includes a processor. The processor is configured to collect plural types of performance information regarding a first data unit. The processor is configured to determine, on basis of the collected plural types of performance information, whether to transfer the first data unit from a first storage device which is under control of a first controller to a second storage device which is positioned as higher than the first storage device. The processor is configured to transfer the first data unit from the first storage device to the second storage device depending on a result of the determination.

Abstract: An apparatus includes a first cache memory, a second cache memory, and a processor coupled to the first cache memory and the second cache memory, and configured to store data in the second cache memory, the data being deleted from the first cache memory, store first data stored in a first address of the storage device, in the second cache memory, in case where the first address is included in first management information and is not included in second management information, according to a request for access to the first address of the storage device, the first management information including an address in the storage device of specific data stored in the storage device, and the second management information including an address in the storage device of data stored in both of the second cache memory and the storage device, and register the first address in the second management information.

Abstract: A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and performs LRU control with the use of the shared queue. The control unit also provides a local queue in the memory space of the shared cache memory. The control unit enqueues a CBE (management information) for a cache page used by a core in a process to the local queue. The control unit dequeues a plurality of CBEs from the local queue upon satisfaction of a predetermined condition, and enqueues the dequeued CBEs to the shared queue.