Abstract: An information processing device includes: a memory; and a processor coupled to the memory and configured to: manage a metatask that creates new metadata, in association with a task, on the basis of metadata set to data to be processed for new data obtained by executing the task on the data to be processed; execute the metatask managed in association with the task when the task is executed on a single or a plurality of pieces of data and create new metadata on the basis of metadata set to each of the single or the plurality of pieces of data; and set the new metadata to new data obtained by executing the task on the single or the plurality of pieces of data.

Abstract: A method of compiling a program that executes a plurality of unit processes in parallel, the method includes: replacing a load instruction of a volatile variable, the volatile variable being a variable included in the program and having a possibility of being overwritten by another unit process, with a beginning load instruction indicating a beginning of a range of transactionization and a load, and an end instruction indicating an ending of the range of the transactionization; moving the beginning load instruction before a position of the load instruction of the volatile variable in the program by instruction scheduling; and generating a beginning instruction indicating a beginning of a range of the transactionization and a load instruction of the volatile variable from the moved beginning load instruction.

Abstract: First and second determination units determine amplitude levels of an input data signal in synchronization with respective first and second clocks, a phase detector detects a phase relationship between the input data signal and the second clock based on the amplitude levels, and first and second phase adjusters adjust phases of the respective first and second clocks according to a detection result of the phase detector. Further, a correction unit corrects a skew generated between the first and second clocks which arrive at the first and second determination units. A correction amount determination unit determines a correction amount corresponding to the skew in the correction unit according to the detection result in the phase detector when a phase difference set between the first and second clocks is made zero.

Abstract: First and second determination units determine amplitude levels of an input data signal in synchronization with respective first and second clocks, a phase detector detects a phase relationship between the input data signal and the second clock based on the amplitude levels, and first and second phase adjusters adjust phases of the respective first and second clocks according to a detection result of the phase detector. Further, a correction unit corrects a skew generated between the first and second clocks which arrive at the first and second determination units. A correction amount determination unit determines a correction amount corresponding to the skew in the correction unit according to the detection result in the phase detector when a phase difference set between the first and second clocks is made zero.

Abstract: A receiver circuit includes: first and second phase adjusters that generate first and second clock signals; first and second determinators that perform binary determination on input data in synchronization with the first and second clock signals; a phase detection circuit that detects a phase on the basis of determination values of the first and the second determinators; a filter that performs filtering on the detected phase and thereby outputs first phase information to the second phase adjuster; an adder that adds a shift amount to the first phase information and thereby outputs second phase information to the first phase adjuster; and a corrector that outputs third phase information for decreasing variation in phase difference of the first clock signal with respect to the second clock signal to the first phase adjuster.

Abstract: An interpolation circuit includes: a first circuit that generates first interpolation data from a plurality of pieces of data among data inputted in time series; a second circuit that generates second interpolation data from the plurality of pieces of data in timing when a part of the data inputted in time series in the first circuit lacks; and a third circuit that adds the second interpolation data to a location in the first interpolation data where the part of the data inputted in time series has lacked.

Abstract: A clock data recovery method includes: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating the first digital signal in accordance with phase information to generate interpolation data; outputting phase difference data indicating a difference in phase of the interpolation data from the sample clock; performing a filtering process on the phase difference data to generate the phase information; performing an equalization process on the interpolation data in accordance with output data; and performing a binary decision on results of the equalization process to generate the output data.

Abstract: A receiver circuit includes: first and second phase adjusters that generate first and second clock signals; first and second determinators that perform binary determination on input data in synchronization with the first and second clock signals; a phase detection circuit that detects a phase on the basis of determination values of the first and the second determinators; a filter that performs filtering on the detected phase and thereby outputs first phase information to the second phase adjuster; an adder that adds a shift amount to the first phase information and thereby outputs second phase information to the first phase adjuster; and a corrector that outputs third phase information for decreasing variation in phase difference of the first clock signal with respect to the second clock signal to the first phase adjuster.

Abstract: A receiver circuit includes a data interpolator to interpolate an input data signal and generate an interpolation data signal, a data determination unit to determine a data determination result of the interpolation data signal, a clock recovery unit to detect phase information based on a data determination result and output an interpolation code determining an interpolation rate to the data interpolator based on the detected phase information, a first interpolator to interpolate the input data signal and generate an interpolation data signal for an eye pattern monitor, a first determination unit for the eye pattern monitor to compare the interpolation data signal with a reference voltage, a match determination unit to determine whether the data determination result of the data determination unit matches a comparison result of the first determination unit, and an eye pattern regenerator to generate an eye pattern based on the phase information and a determination result.

Abstract: A clock data recovery method includes: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating the first digital signal in accordance with phase information to generate interpolation data; outputting phase difference data indicating a difference in phase of the interpolation data from the sample clock; performing a filtering process on the phase difference data to generate the phase information; performing an equalization process on the interpolation data in accordance with output data; and performing a binary decision on results of the equalization process to generate the output data.

Abstract: A receiver circuit includes a data interpolator to interpolate an input data signal and generate an interpolation data signal, a data determination unit to determine a data determination result of the interpolation data signal, a clock recovery unit to detect phase information based on a data determination result and output an interpolation code determining an interpolation rate to the data interpolator based on the detected phase information, a first interpolator to interpolate the input data signal and generate an interpolation data signal for an eye pattern monitor, a first determination unit for the eye pattern monitor to compare the interpolation data signal with a reference voltage, a match determination unit to determine whether the data determination result of the data determination unit matches a comparison result of the first determination unit, and an eye pattern regenerator to generate an eye pattern based on the phase information and a determination result.

Abstract: An interpolation circuit includes: a generation circuit that generates interpolation data from a plurality of pieces of input data, using an interpolation coefficient, among input data inputted in time series including a data point and a transition point; a detection circuit that detects that the input data lacks at the data point; and a coefficient circuit that changes the interpolation coefficient for each given data interval, and skips a position for changing the interpolation coefficient to the transition point when the detection circuit detects the lack of the input data.

Abstract: An interpolation circuit includes: a generation circuit that generates interpolation data from a plurality of pieces of input data, using an interpolation coefficient, among input data inputted in time series including a data point and a transition point; a detection circuit that detects that the input data lacks at the data point; and a coefficient circuit that changes the interpolation coefficient for each given data interval, and skips a position for changing the interpolation coefficient to the transition point when the detection circuit detects the lack of the input data.

Abstract: An interpolation circuit includes: a first circuit that generates first interpolation data from a plurality of pieces of data among data inputted in time series; a second circuit that generates second interpolation data from the plurality of pieces of data in timing when a part of the data inputted in time series in the first circuit lacks; and a third circuit that adds the second interpolation data to a location in the first interpolation data where the part of the data inputted in time series has lacked.

Abstract: A timing signal generator circuit includes a DA converter converting an input digital value into an analog voltage, and a VT converter converting the analog voltage into a corresponding delay time. The DA converter includes a current source circuit, which supplies a current (n×Is) (“n” is a number corresponding to the input digital value) selected from a total supply current (N×Is) as a current Iout to the resistors, and supplies the remaining current (N?n)×Is as a current Idump to the resistors, outputs a voltage across the resistors as an analog voltage Vdac, and outputs a voltage across the resistor as a reset voltage Vreset. The VT converter charges the integration capacitor with a constant current from the constant current source by using the reset voltage as an initial voltage, and outputs a timing signal when the integral voltage exceeds the analog voltage.

Abstract: A timing signal generator circuit includes a DA converter converting an input digital value into an analog voltage, and a VT converter converting the analog voltage into a corresponding delay time. The DA converter includes a current source circuit, which supplies a current (n×Is) (“n” is a number corresponding to the input digital value) selected from a total supply current (N×Is) as a current Iout to the resistors, and supplies the remaining current (N?n)×Is as a current Idump to the resistors, outputs a voltage across the resistors as an analog voltage Vdac, and outputs a voltage across the resistor as a reset voltage Vreset. The VT converter charges the integration capacitor with a constant current from the constant current source by using the reset voltage as an initial voltage, and outputs a timing signal when the integral voltage exceeds the analog voltage.