Patents by Inventor Takushi Nishiya

Takushi Nishiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060248427
    Abstract: A random seed scramble for preventing the deterioration of a medium is applied to the next generation optical disk. A seed is stored to a BIS area. ID or an EDC is checked to hold interchangeability before and after scramble release. When no error is generated in data before the scramble release, it is recognized as an unscrambled disk. In contrast to this, when no error is generated in data after the scramble release, it is recognized as a scrambled disk. An information storing area showing an area to be rewritten by performing the scramble and an area to be rewritten without performing the scramble is arranged.
    Type: Application
    Filed: June 20, 2006
    Publication date: November 2, 2006
    Inventors: Yukari Katayama, Takeshi Maeda, Harukazu Miyamoto, Takushi Nishiya, Takatoshi Kato, Shigeki Taira, Osamu Kawamae, Taku Hoshizawa
  • Patent number: 6980385
    Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: December 27, 2005
    Assignees: Hitachi Video and Information System, Inc., Hitachi Global Storage Technologies Japan, Ltd.
    Inventors: Takatoshi Kato, Takushi Nishiya, Hideyuki Yamakawa, Takashi Nara, Nobuaki Nakai, Hiroshi Ide, Shintaro Suzumura, Terumi Takashi
  • Patent number: 6954876
    Abstract: Defect management information of a disk apparatus is read efficiently. Pieces of defective track information, which each indicate existence of defective tracks for a group of a plurality of tracks, are stored being associated with physical track numbers. And, pieces of defect information on defective tracks are stored in predetermined groups. Further, pieces of pointer information that indicate start addresses of storage address for the above-mentioned predetermined groups are stored. When a processing means receives an instruction of read or write to a track of a storage medium, the processing means refers to a piece of defective track information based on the above-mentioned addresses. When existence of a defective track is indicated, the processing means refers to a piece of pointer information corresponding to the group relating to the referred piece of defective track information.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: October 11, 2005
    Assignee: Hitachi Global Storage Technologies Japan, Ltd.
    Inventors: Hitoshi Ogawa, Takushi Nishiya, Soichi Isono, Tomoki Oura
  • Publication number: 20050041316
    Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
    Type: Application
    Filed: August 10, 2004
    Publication date: February 24, 2005
    Inventors: Takatoshi Kato, Takushi Nishiya, Hideyuki Yamakawa, Takashi Nara, Nobuaki Nakai, Hiroshi Ide, Shintaro Suzumura, Terumi Takashi
  • Patent number: 6791776
    Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 14, 2004
    Assignees: Hitachi, Ltd., Hitachi Video and Information System, Inc.
    Inventors: Takatoshi Kato, Takushi Nishiya, Hideyuki Yamakawa, Takashi Nara, Nobuaki Nakai, Hiroshi Ide, Shintaro Suzumura, Terumi Takashi
  • Publication number: 20030135798
    Abstract: A random seed scramble for preventing the deterioration of a medium is applied to the next generation optical disk. A seed is stored to a BIS area. ID or an EDC is checked to hold interchangeability before and after scramble release. When no error is generated in data before the scramble release, it is recognized as an unscrambled disk. In contrast to this, when no error is generated in data after the scramble release, it is recognized as a scrambled disk. An information storing area showing an area to be rewritten by performing the scramble and an area to be rewritten without performing the scramble is arranged.
    Type: Application
    Filed: December 12, 2002
    Publication date: July 17, 2003
    Inventors: Yukari Katayama, Takeshi Maeda, Harukazu Miyamoto, Takushi Nishiya, Takatoshi Kato, Shigeki Taira, Osamu Kawamae, Taku Hoshizawa
  • Publication number: 20020071193
    Abstract: Defect management information of a disk apparatus is read efficiently. Pieces of defective track information, which each indicate existence of defective tracks for a group of a plurality of tracks, are stored being associated with physical track numbers. And, pieces of defect information on defective tracks are stored in predetermined groups. Further, pieces of pointer information that indicate start addresses of storage address for the above-mentioned predetermined groups are stored. When a processing means receives an instruction of read or write to a track of a storage medium, the processing means refers to a piece of defective track information based on the above-mentioned addresses. When existence of a defective track is indicated, the processing means refers to a piece of pointer information corresponding to the group relating to the referred piece of defective track information.
    Type: Application
    Filed: December 10, 2001
    Publication date: June 13, 2002
    Inventors: Hitoshi Ogawa, Takushi Nishiya, Soichi Isono, Tomoki Oura
  • Patent number: 6373407
    Abstract: The computer system includes a host system, a recording medium, and a digital signal decoder connected to the host system and the recording medium. The digital signal decoder receives M-bit data and generates an N-bit code word from the M-bit data. The number of consecutive bits of 1 in the code word is not larger than a first predetermined number K, and the number of consecutive bits of 0 is not larger than a second predetermined number L. When data is recorded/reproduced by a method such as NRZI (Non-Return to Zero Inverted), or the like, there is a defect in that the number of transitions of data is larger in a code with a high data encoding rate, and the run length of zero is long thereby increasing the data decoding error rate with the recording/reproducing of data. In the digital signal decoder according to the present invention, any code word includes at most 3 consecutive bits of 1, and at most 11 consecutive bits of 0, so that the data decoding error rate can be reduced.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: April 16, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takushi Nishiya, Tatsuya Hirai, Seiichi Mita, Takashi Nara, Yoichi Uehara, Hiroshi Ide, Kyoko Tsukano, Yoshiju Watanabe
  • Patent number: 6326838
    Abstract: A transconductance control circuit is composed of a replica transconductance amplifier and resistance, a reference voltage source, first selectors, a differential amplifier, a voltage-current translate circuit with characteristics equal to the transconductance amplifier which constitutes analog filters. A first switch of the first selectors is connectable for the reference voltage source, and every constant period is made to connect it using clocks at the reference voltage source. A second switch of second selectors is connectable for plural capacitors, and every constant period is made to connect it using clocks at the capacitors.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: December 4, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Kimura, Takushi Nishiya, Takatoshi Kato, Takashi Nara, Seiichi Mita
  • Publication number: 20010043416
    Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
    Type: Application
    Filed: February 28, 2001
    Publication date: November 22, 2001
    Inventors: Takatoshi Kato, Takushi Nishiya, Hideyuki Yamakawa, Takashi Nara, Nobuaki Nakai, Hiroshi Ide, Shintaro Suzumura, Terumi Takashi
  • Patent number: 5940416
    Abstract: A calculation concerning the input of a signal is removed from a branch metric calculation processing on a trellis diagram of an extended partial response class, and the calculation of branch metrics and the selection of survivor paths can be carried out by the subtraction of the survivor paths and the comparison of constants.
    Type: Grant
    Filed: June 24, 1997
    Date of Patent: August 17, 1999
    Assignee: Hitachi Ltd.
    Inventors: Takushi Nishiya, Hideyuki Yamakawa, Shoichi Miyazawa, deceased, Seiichi Mita, Yoichi Uehara, Takashi Nara, Akihiko Hirano
  • Patent number: 5844741
    Abstract: A system for reproducing data recorded on a magnetic recording medium at high density is provided as a simple configuration. Quadripartite reproduction data is output from a Viterbi detection circuit to an adder, which then subtracts the quadripartite reproduction data from a signal before PR4-ML method data determination. An adder is used to perform a (1+D) process for the result. An error signal pattern detection circuit performs maximum likelihood estimation for an PR4-ML method detection error. Further, when a detected determination error matches an actual reproduction data string, a data correction circuit corrects the reproduction data string.
    Type: Grant
    Filed: October 27, 1995
    Date of Patent: December 1, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hideyuki Yamakawa, Takushi Nishiya, Takashi Nara, Terumi Takashi
  • Patent number: 5774470
    Abstract: A playback signal processing circuit for reducing decode errors and enabling high-density digital magnetic recording and a digital magnetic recording reproducing unit using the playback signal processing circuit are provided. An estimated waveform generation circuit uses the decoding result of a PRML channel to generate an ideal playback signal waveform. A subtractor provides a waveform representing a difference between the waveform and an actual playback signal. There is a high probability that error bits will occur at an interval of two or four bits because of the nature of GCR code and maximum-likelihood decoding; in the error state of each bit, one bit is incremented by one with respect to the correct bit value and the other signal bit is decremented by one. From this fact, an error detection circuit discriminates an error difference waveform pattern and an error discrimination circuit detects an error bit interval, whereby an error correction circuit carries out error bit correction.
    Type: Grant
    Filed: September 6, 1995
    Date of Patent: June 30, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Takushi Nishiya, Shoichi Miyazawa, Kazutoshi Ashikawa, Ryushi Shimokawa, Seiichi Mita
  • Patent number: 5265222
    Abstract: A symbolization apparatus which includes a membership function memory unit for storing a membership function used in fuzzy logic processing. In the symbolization apparatus a process condition change pattern is converted into an ambiguous symbol in order to build up a system capable of effecting an inference and decision approximate to a skilled operator against an object process. A process condition value memory is disclosed for holding a measurement of the process condition value and a process operation amount, a control history memory unit for storing operations and values converted into symbolic expressions, control units and a knowledge base for storing the information relating to the casual relations between the process control values and the process conditions. The process control system and a control support system comprise the function of condition identification approximate to that of a skilled operator by the use of the symbolization apparatus.
    Type: Grant
    Filed: November 23, 1990
    Date of Patent: November 23, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Takushi Nishiya, Motohisa Funabashi, Hiromitsu Kurisu, Mikio Yoda, Kazuo Kera
  • Patent number: 5175797
    Abstract: A method and apparatus of a learning type decision support system are provided for improved acquisition of a priori knowledge from the system object and expression of non-linear structures in the object. The system is comprised of a learning module and an executing module for outputting advice and process manipulate command values to system users by receiving input data comprising on-line data and file data.
    Type: Grant
    Filed: August 31, 1990
    Date of Patent: December 29, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Motohisa Funabashi, Takushi Nishiya, Masahiro Oba, Mikio Yoda, Kazuo Kera, Kiyomi Mori
  • Patent number: 5127063
    Abstract: In order to easily identify a pattern of time-series state changes based on measured information so as to facilitate representation of edge portions of an image, features extracted in a form of expansion coefficients of polynomials from the measured information are translated into abstract expressions so as to detect from the measured information significant control information which has not been used in the conventional technology, and features extracted in a form of expansion coefficients from brightness changes in the vicinity of each pixel constituting image data are translated into abstract expression.
    Type: Grant
    Filed: September 20, 1989
    Date of Patent: June 30, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Takushi Nishiya, Motohisa Funabashi
  • Patent number: 5109431
    Abstract: An apparatus for comparing a data pattern with standard patterns to discriminate the data pattern retrieves vector series of the standard patterns associated with the data pattern. Categorized names are assigned to data of the vector series so as to be respectively associated with elements of the data pattern, thereby determining a similarity degree and a scale factor between the vector series.
    Type: Grant
    Filed: May 21, 1990
    Date of Patent: April 28, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Takushi Nishiya, Motohisa Funabashi, Kazuo Kera
  • Patent number: 4825393
    Abstract: Points on a pair of images obtained by imaging an object are finely corresponded in order to precisely measure the three-dimensional position of the object. For this purpose, attractive forces corresponding to features of the images are calculated, and the degree of correspondence between the points on the pair of images is evaluated relying upon the magnitude of the attractive force, in order to determine the corresponding points and to calculate the position of the object relying upon the thus determined corresponding points. Further, an occluded region which contains no corresponding point is detected and is removed, in order to further improve the precision for measuring the position.
    Type: Grant
    Filed: April 22, 1987
    Date of Patent: April 25, 1989
    Assignee: Hitachi, Ltd.
    Inventor: Takushi Nishiya
  • Patent number: 4792694
    Abstract: A method of forming a three-dimensional stereo vision is disclosed in which, in order to prevent the erroneous detection of an object point in the conventional method using two image focusing lens systems, three image points of an object point formed by logically and/or physically selecting three image focusing lens systems and three image sensing surfaces from a multiplicity of image points on an image sensing surface by using the fact that a positional relation among three image points of the same object point is similar to the positional relation among the three image focusing lens systems, and the positional information of three selected image points on the image sensing surface is used for obtaining three-dimensional distance information of the object point.
    Type: Grant
    Filed: April 17, 1986
    Date of Patent: December 20, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Shioya, Motohisa Funabashi, Takushi Nishiya