Patents by Inventor Takuya Ariki

Takuya Ariki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11177277
    Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: November 16, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
  • Patent number: 11081192
    Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 3, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Publication number: 20210142858
    Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
  • Publication number: 20210134375
    Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Publication number: 20210134828
    Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
  • Patent number: 10991429
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: April 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Fumiaki Toyama, Takuya Ariki
  • Patent number: 10984874
    Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
  • Patent number: 10885984
    Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Patent number: 10854619
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: December 1, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Publication number: 20200294599
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Inventors: Hiroyuki OGAWA, Fumiaki TOYAMA, Takuya ARIKI
  • Patent number: 10734080
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: August 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Patent number: 10720213
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Fumiaki Toyama, Takuya Ariki
  • Publication number: 20200185039
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Publication number: 20200185397
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Publication number: 20190057741
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Application
    Filed: December 19, 2016
    Publication date: February 21, 2019
    Inventors: Hiroyuki OGAWA, Fumiaki Toyama, Takuya Ariki
  • Publication number: 20170243650
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 24, 2017
    Inventors: Hiroyuki OGAWA, Fumiaki TOYAMA, Takuya ARIKI
  • Patent number: 9721663
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: August 1, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Fumiaki Toyama, Takuya Ariki
  • Patent number: 9595535
    Abstract: Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact via structures to the electrically conductive layers for word lines. Via cavities in a dielectric material portion overlying stepped surfaces of the electrically conductive layers can be filled with a conductive material and recessed to form contact via structures. After forming lower active regions in the recesses, gate electrodes can be formed and patterned to form openings in areas overlying the contact via structures. Gate dielectrics can be formed on the sidewalls of the openings, and transistor channels can be formed inside the openings of the gate electrodes. Upper active regions can be formed over the transistor channels.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: March 14, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Makoto Yoshida, Kazutaka Yoshizawa, Takuya Ariki, Toru Miwa
  • Patent number: 8395434
    Abstract: A level shifter circuit is presented that can apply a negative voltage level to non-selected blocks while still being able to drive a high positive level when selected. An exemplary embodiment presents a negative level shifter that is not susceptible to low voltage pfet breakdown. This allows for a high voltage level shifter (transfer gate) that can drive a negative level for unselected blocks and, when enabled for a selected block, can still drive a positive high voltage level. By using a pair of low voltage PMOS device whose n-wells share the same level as other PMOS transistors in the design, layout area can be minimized. The gates of this pair of PMOSs are connected to VSS, thereby preventing these low voltage PMOS devices from thin oxide breakdown.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: March 12, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Qui Vi Nguyen, Takuya Ariki, Jongmin Park
  • Patent number: 8076911
    Abstract: A voltage regulator includes a voltage regulator unit configured to output a step voltage and a damping resistance switching unit coupled between a load and an output node of the voltage regulator and configured to select an optimal damping resistance value based on a required load capacity.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Takuya Ariki