Abstract: A power-on reset system comprises one-shot pulse generator for generating a one-shot pulse signal in response to a change in the power supply potential, a flip-flop to be set to operate by a one shot pulse signal and a timer to be activated by an output signal of said flip-flop operating as an enable signal for timing a given period of time. An output signal of said timer operates to reset the flip-flop so that the output of said flip-flop is utilized as a system reset signal. The timer includes an oscillator and a counter for counting oscillation signals. A voltage step-up means has an input responsive to the oscillation signals. With such an arrangement, the overall surface area of an LSI incorporating the system is minimized and a sufficiently long reset period is ensured for it.