Patents by Inventor Takuya Hachida

Takuya Hachida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9030237
    Abstract: A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: May 12, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takuya Hachida, Yasushi Sasaki, Yuhichiroh Murakami, Etsuo Yamamoto
  • Patent number: 8970565
    Abstract: A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: March 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takuya Hachida, Yuhichiroh Murakami, Shige Furuta, Makoto Yokoyama, Yasushi Sasaki
  • Patent number: 8717273
    Abstract: A memory-type liquid crystal display device includes a liquid crystal panel including memory circuits, and conducts a refresh operation more than once during a display holding period after rewriting of a screen. The memory-type liquid crystal display device increases at least one of (i) a frequency at which the screen is rewritten and (ii) a frequency at which the refresh operation is conducted during the display holding period as an intensity of light received by the liquid crystal panel increases. This allows the memory-type liquid crystal display device to reduce power consumption while keeping its display quality.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 6, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takuya Hachida, Yasushi Sasaki, Yuhichiroh Murakami, Shuji Nishi, Seijirou Gyouten
  • Publication number: 20130147524
    Abstract: A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.
    Type: Application
    Filed: September 1, 2011
    Publication date: June 13, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Takuya Hachida, Yasushi Sasaki, Yuhichiroh Murakami, Etsuo Yamamoto
  • Publication number: 20130094166
    Abstract: A plurality of display panels (10A and 10B) are provided on a single substrate (2). Data signal lines (11A), scanning signal lines (12A), a data signal line drive circuit (20A) for driving the data signal lines (11A), and a scanning signal line drive circuit (30A) for driving the scanning signal lines (12A) are provided for the display panel (10A). Data signal lines (11B), scanning signal lines (12B), a data signal line drive circuit (20B) for driving the data signal lines (11B), and a scanning signal line drive circuit (30B) for driving the scanning signal lines (12B) are provided for the display panel (10B). Input signal lines (17A and 17B) are provided so as not intersect each other in a plan view. This allows a reduction in power consumption and an increase in flexibility in design in a display panel which includes a plurality of display panels on a single substrate.
    Type: Application
    Filed: May 11, 2011
    Publication date: April 18, 2013
    Inventors: Makoto Yokoyama, Eiji Matsuda, Takahiro Yamaguchi, Shuji Nishi, Takuya Hachida, Seijirou Gyouten
  • Publication number: 20130076607
    Abstract: A plurality of the display panels (10A and 10B) are provided on a single substrate. For each of the plurality of the display panels (10A and 10B), there are provided data signal lines (11A and 11B), scanning signal lines (12A and 12B), data signal line drive circuits (20A and 20B) which drive the respective data signal lines (11A and 11B) and scanning signal line drive circuits (30A and 30B) which drive the respective scanning signal lines (12A and 12B). This allows achievement of lower electric power consumption and greater design freedom in a display device including a plurality of display panels which are provided on a single substrate.
    Type: Application
    Filed: May 11, 2011
    Publication date: March 28, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Eiji Matsuda, Makoto Yokoyama, Shuji Nishi, Takahiro Yamaguchi, Takuya Hachida, Seijirou Gyouten
  • Publication number: 20120188218
    Abstract: A memory-type liquid crystal display device includes a liquid crystal panel including memory circuits, and conducts a refresh operation more than once during a display holding period after rewriting of a screen. The memory-type liquid crystal display device increases at least one of (i) a frequency at which the screen is rewritten and (ii) a frequency at which the refresh operation is conducted during the display holding period as an intensity of light received by the liquid crystal panel increases. This allows the memory-type liquid crystal display device to reduce power consumption while keeping its display quality.
    Type: Application
    Filed: June 25, 2010
    Publication date: July 26, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takuya Hachida, Yasushi Sasaki, Yuhichiroh Murakami, Shuji Nishi, Seijirou Gyouten
  • Publication number: 20120105395
    Abstract: A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.
    Type: Application
    Filed: March 18, 2010
    Publication date: May 3, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takuya Hachida, Yuhichiroh Murakami, Shige Furuta, Makoto Yokoyama, Yasushi Sasaki