Patents by Inventor Takuya Hamaguchi
Takuya Hamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11479209Abstract: An input information management system for a vehicle that can be used by using each of a plurality of electronic keys, the system managing input information that is input by a user, where the system includes a key information acquisition unit that acquires and stores key information of an electronic key, when an operation is performed on the vehicle using the electronic key, and an input information erasure unit that erases the input information that is stored in a storage device, where, when the key information is acquired by the key information acquisition unit, the input information erasure unit compares current key information that is acquired with last key information that is last stored by the key information acquisition unit before acquisition of the current key information, and erases the input information that is stored in the storage device on a basis of a result of the comparison.Type: GrantFiled: March 12, 2020Date of Patent: October 25, 2022Assignee: HONDA MOTOR CO., LTD.Inventors: Shigenori Hiruta, Yuji Nishikawa, Takuya Hamaguchi, Hiroyuki Hayashi
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Publication number: 20200307516Abstract: An input information management system for a vehicle that can be used by using each of a plurality of electronic keys, the system managing input information that is input by a user, where the system includes a key information acquisition unit that acquires and stores key information of an electronic key, when an operation is performed on the vehicle using the electronic key, and an input information erasure unit that erases the input information that is stored in a storage device, where, when the key information is acquired by the key information acquisition unit, the input information erasure unit compares current key information that is acquired with last key information that is last stored by the key information acquisition unit before acquisition of the current key information, and erases the input information that is stored in the storage device on a basis of a result of the comparison.Type: ApplicationFiled: March 12, 2020Publication date: October 1, 2020Inventors: Shigenori Hiruta, Yuji Nishikawa, Takuya Hamaguchi, Hiroyuki Hayashi
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Patent number: 10461049Abstract: An aluminum electrode (2) is provided on a semiconductor device (1). A metallic film (3) for a solder joint is provided on the aluminum electrode (2). The organic protective film (4) is apart from the metallic film (3). An interval between the organic protective film (4) and the metallic film (3) is equal to or greater than half of a thickness of the organic protective film (4). Thus, even when the organic protective film (4) is deformed during sinter joining, the stress is not transmitted to the metallic film (3). Therefore, it is possible to prevent the solder connection metallic film (3) from cracking.Type: GrantFiled: December 14, 2015Date of Patent: October 29, 2019Assignee: Mitsubishi Electric CorporationInventors: Takuya Hamaguchi, Yosuke Nakata, Seiya Nakano, Masayoshi Tarutani
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Publication number: 20180190605Abstract: An aluminum electrode (2) is provided on a semiconductor device (1). A metallic film (3) for a solder joint is provided on the aluminum electrode (2). The organic protective film (4) is apart from the metallic film (3). An interval between the organic protective film (4) and the metallic film (3) is equal to or greater than half of a thickness of the organic protective film (4). Thus, even when the organic protective film (4) is deformed during sinter joining, the stress is not transmitted to the metallic film (3). Therefore, it is possible to prevent the solder connection metallic film (3) from cracking.Type: ApplicationFiled: December 14, 2015Publication date: July 5, 2018Applicant: Mitsubishi Electric CorporationInventors: Takuya HAMAGUCHI, Yosuke NAKATA, Seiya NAKANO, Masayoshi TARUTANI
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Patent number: 9153502Abstract: A semiconductor chip testing method includes: (a) testing the electrical characteristics of each of semiconductor chips in the form of wafers or in the form of chips formed on a predetermined number of semiconductor wafers having certain relationship, and determining if the semiconductor chip is non-defective or defective; (b) calculating a percentage of semiconductor chips determined to be defective as a fraction defective for each of wafer addresses based on determination results about the semiconductor chips on the predetermined number of semiconductor wafers, the wafer addresses indicating the respective positions of the semiconductor chips on the semiconductor wafers; and (c) changing a determination result about a semiconductor chip determined to be non-defective to defective, the semiconductor chip being at a wafer address determined to have a fraction defective at a threshold or higher than the threshold.Type: GrantFiled: June 12, 2012Date of Patent: October 6, 2015Assignee: Mitsubishi Electric CorporationInventors: Takuya Hamaguchi, Tetsujiro Tsunoda, Shoko Kanazawa
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Publication number: 20130080088Abstract: A semiconductor chip testing method includes: (a) testing the electrical characteristics of each of semiconductor chips in the form of wafers or in the form of chips formed on a predetermined number of semiconductor wafers having certain relationship, and determining if the semiconductor chip is non-defective or defective; (b) calculating a percentage of semiconductor chips determined to be defective as a fraction defective for each of wafer addresses based on determination results about the semiconductor chips on the predetermined number of semiconductor wafers, the wafer addresses indicating the respective positions of the semiconductor chips on the semiconductor wafers; and (c) changing a determination result about a semiconductor chip determined to be non-defective to defective, the semiconductor chip being at a wafer address determined to have a fraction defective at a threshold or higher than the threshold.Type: ApplicationFiled: June 12, 2012Publication date: March 28, 2013Applicant: Mitsubishi Electric CorporationInventors: Takuya HAMAGUCHI, Tetsujiro Tsunoda, Shoko Kanazawa
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Patent number: 8390097Abstract: An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other portions, the width extending in the direction intersecting the trenches. This configuration allows for an increase in the emitter ballast resistance of the emitter diffusion layers, resulting in enhanced resistance to electrical breakdown due to short circuit.Type: GrantFiled: January 17, 2007Date of Patent: March 5, 2013Assignee: Mitsubishi Electric CorporationInventors: Takuya Hamaguchi, Hideki Haruguchi, Tetsujiro Tsunoda
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Publication number: 20110024896Abstract: A power semiconductor device that can reduce the mounting area thereof will be provided. A first metal plate is connected to a first power terminal of a power chip. A second metal plate facing the first metal plate is connected to a second power terminal of the power chip. An insulating cover coats the power chip from outside of the first and second metal plates. An exterior signal terminal connected to the signal terminal of the power chip is derived from an upper surface of the insulating cover. The first and second metal plate respectively includes first and second exterior electric power terminals derived from a lower surface of the insulating cover. The first and second exterior electric power terminals are bent to opposite directions.Type: ApplicationFiled: July 7, 2008Publication date: February 3, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Tetsujiro Tsunoda, Takuya Hamaguchi
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Patent number: 7777249Abstract: A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.Type: GrantFiled: May 25, 2007Date of Patent: August 17, 2010Assignee: Mitsubishi Electric CorporationInventors: Takuya Hamaguchi, Hideki Haruguchi, Tetsujiro Tsunoda
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Publication number: 20080173893Abstract: A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.Type: ApplicationFiled: May 25, 2007Publication date: July 24, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuya Hamaguchi, Hideki Haruguchi, Tetsujiro Tsunoda
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Publication number: 20080079066Abstract: An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other portions, the width extending in the direction intersecting the trenches. This configuration allows for an increase in the emitter ballast resistance of the emitter diffusion layers, resulting in enhanced resistance to electrical breakdown due to short circuit.Type: ApplicationFiled: January 17, 2007Publication date: April 3, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuya Hamaguchi, Hideki Haruguchi, Tetsujiro Tsunoda
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Patent number: 5631753Abstract: The black matrix substrate used for a flat display such as a liquid crystal display panel, an imager such as CCD or a color filter such as a color sensor comprises a transparent substrate and a light-shielding layer formed on the transparent substrate, and the light-shielding layer contains metallic particles inside thereof, whereby the light-shielding layer can show high light-shielding properties and a low reflectance. In the liquid crystal display panel comprising substrates facing each other and a liquid crystal sealed between the substrates, a semiconductor device provided on one of the substrates has a light-shielding layer which contains metallic particles inside thereof, whereby the semiconductor device can be effectively protected and the liquid crystal display panel has a high contrast.Type: GrantFiled: April 4, 1995Date of Patent: May 20, 1997Assignee: Dai Nippon Printing Co., Ltd.Inventors: Takuya Hamaguchi, Hiroyuki Kusukawa, Yasutomo Teshima, Ryutaro Harada, Satoshi Mitamura
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Patent number: 5554451Abstract: An optical data recording medium of the present invention includes: a substrate; a reflective material layer formed of light-reflective material, the reflective material layer being provided over the substrate; and an optical data recording layer for optically recording data therein and for optically reproducing the data therefrom, the optical data recording layer being formed over the reflective material layer. The reflective material layer is patterned so that the light-reflective material may be partly removed therefrom for selectively allowing a light beam irradiated on the substrate to pass therethrough to reach the optical data recording layer.Type: GrantFiled: September 28, 1992Date of Patent: September 10, 1996Assignee: Brother Kogyo Kabushiki KaishaInventors: Kazunari Taki, Yumiko Ohashi, Takuya Hamaguchi, Hideo Maruyama, Riki Matsuda
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Patent number: 5224090Abstract: The optical recording member according to the present invention includes an information recording pattern consisting of high reflectance portions and low reflectance portions formed on a substrate. During reading of information, discrimination of recording information is done by detecting the difference in light reflectance between the above respective portions. In this case, the low reflectance portions are roughened on their surface and have light scattering property, and therefore the difference in light reflectance can be well detected. Further, the method for preparing the optical recording member according to the present invention can be practiced according to relatively simple means of the surface roughening step of the above low reflectance portions and yet according to a precise and rapid method, and therefore it is suitable for bulk production on an industrial scale.Type: GrantFiled: September 10, 1992Date of Patent: June 29, 1993Assignee: Dai Nippon Insatsu Kabushiki KaishaInventors: Kazuo Umeda, Masaaki Asano, Minoru Utsumi, Takuya Hamaguchi, Takeshi Matsumoto, Yuji Kondo