Abstract: A delay lock loop circuit and its delay amount calibration method is disclosed. An initially set value of a counter is determined by a technique which replaces measurement of a delay amount, whereby a time required for calibration of a delay circuit can be reduced. One counter set value of a plurality of counter set values is loaded, a delay lock loop circuit is switched to a lock mode, and a sequence circuit of a cycle slip detection circuit is reset. Thereafter, a cycle slip detection signal output from the sequence circuit is read, and based on the reading, it is judged whether or not an output signal of a delay circuit causes cycle slip. If the cycle slip is caused, the counter set value is switched. If any cycle slip is not caused, the counter set value is locked, thereby terminating the process.

Abstract: A delay circuit includes a first delay element, a second delay element, and an initializing section that measures a delay amount generated by the first delay element with respect to each delay setting value. The initializing section includes a first loop path that inputs an output signal of the first delay element into the first delay element and a second loop path that inputs an output signal of the second delay element into the second delay element. The initialization section includes a first measuring section that sequentially sets delay setting values mutually different from the delay setting value in the first delay element and sequentially measures delay amounts in the first delay element, a second measuring section that measures a delay amount in the second delay element, and a delay amount computing section that corrects a delay amount measured by the first measuring section.

Abstract: Provided is a variable delay circuit outputting an output signal delayed with respect to an input signal by a designated delay time, including: a delay controller outputting a control voltage according to the delay time; a MOS transistor receiving the control voltage at a gate, and outputs a drain current according to the control voltage; a correction section connected in parallel to a source and a drain of the current controlling MOS transistor, and outputs a correction current on a monotonic decrease as the drain current increases in a range larger than a predetermined boundary current within a normal usage range of the drain current; and a delay element running an output current resulting from adding the correction current to the drain current, between the delay element and an output terminal of the variable delay circuit, in changing a signal value of the output signal according to the input signal.

Abstract: To provide a load fluctuation correction circuit having a function of correcting the change in the current consumption amount due to the change in the driving state of a logic circuit, thereby suppressing the change in the source voltage applied to the logic circuit.

Abstract: A method replaces a delay amount measurement in which an initially set value of a counter is determined by a technique which replaces measurement of a delay amount, whereby a time required for calibration of a delay circuit can be reduced. One counter set value of a plurality of counter set values is loaded, a delay lock loop circuit is switched to a lock mode, and a sequence circuit of a cycle slip detection circuit is reset. Thereafter, a cycle slip detection signal output from the sequence circuit is read, and on the basis of this cycle slip detection signal, it is judged whether or not an output signal of a delay circuit causes cycle slip. If the cycle slip is caused, the counter set value is switched. On the other hand, if any cycle slip is not caused, the counter set value is locked, thereby terminating the process.

Abstract: Provided is a variable delay circuit outputting an output signal delayed with respect to an input signal by a designated delay time, including: a delay controller outputting a control voltage according to the delay time; a MOS transistor receiving the control voltage at a gate, and outputs a drain current according to the control voltage; a correction section connected in parallel to a source and a drain of the current controlling MOS transistor, and outputs a correction current on a monotonic decrease as the drain current increases in a range larger than a predetermined boundary current within a normal usage range of the drain current; and a delay element running an output current resulting from adding the correction current to the drain current, between the delay element and an output terminal of the variable delay circuit, in changing a signal value of the output signal according to the input signal.

Abstract: There is provided a delay circuit including a first delay element, a second delay element, and an initializing section that measures a delay amount generated by the first delay element with respect to each delay setting value and initializes the first delay element. The initializing section includes: a first loop path that inputs an output signal of the first delay element into the first delay element; a second loop path that inputs an output signal of the second delay element into the second delay element; a first measuring section that sequentially sets delay setting values mutually different from the delay setting value in the first delay element and sequentially measures delay amounts in the first delay element; a second measuring section that measures a delay amount in the second delay element; and a delay amount computing section that corrects a delay amount measured by the first measuring section.

Abstract: To provide a load fluctuation correction circuit having a function of correcting the change in the current consumption amount due to the change in the driving state of a logic circuit, thereby suppressing the change in the source voltage applied to the logic circuit.