Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

Abstract: Each input binary digit of an input serial bit string having a referential word in a referential word time period is sampled N times to produce a plurality of over-sampled binary digits corresponding to a first group of sampling operations, a second group of sampling operations,--, an N-th group of sampling operations, and the over-sampled binary digits are divided to N divided bit strings corresponding to the N groups of sampling operations respectively. Because each divided bit string having the referential word is correctly sampled at high probability, a word start position of the referential word in each divided bit string is detected, one divided bit string correctly sampled at the highest probability is selected, and a string of words starting from the word start position is retrieved from the selected divided bit string and is output.

Abstract: Each input binary digit of an input serial bit string having a referential word in a referential word time period is sampled N times to produce a plurality of over-sampled binary digits corresponding to a first group of sampling operations, a second group of sampling operations, --, an N-th group of sampling operations, and the over-sampled binary digits are divided to N divided bit strings corresponding to the N groups of sampling operations respectively. Because each divided bit string having the referential word is correctly sampled at high probability, a word start position of the referential word in each divided bit string is detected, one divided bit string correctly sampled at the highest probability is selected, and a string of words starting from the word start position is retrieved from the selected divided bit string and is output.

Abstract: A serial data receiving circuit includes a serial-to-parallel converter and a data selector. The serial-to-parallel converter converts the oversampled data fed from an oversampling circuit to m×n bit parallel data. The data selector, receiving (m×n+&agr;) bits of data simultaneously from the serial-to-parallel converter, where &agr; is a natural number indicating the bit number of the data selected from the previous and/or subsequent oversampled data to be added to the m×n-bit data, evaluates all the (m×n+&agr;) bits of data as candidates to be likely selected, and outputs the n-bit parallel data from the (m×n+&agr;) bits of data. The serial data receiving circuit can output the right data in spite of jitter included in the data or clock signal.

Abstract: Power supply voltage step-down circuitry comprises a control unit for enabling either a first voltage step-down unit or a second voltage step-down unit according to a control signal applied thereto, a voltage checking unit for checking whether or not the value of a voltage generated by a power supply is equal to or greater than a predetermined value, and for furnishing a checking result signal at a predetermined level when the value of the voltage generated by the power supply is equal to or greater than a predetermined value, and a switching unit for connecting either the power supply or an output of the first step-down unit with a receiver, such as a ROM, according to whether or not the checking result signal from the voltage checking unit is at the predetermined level.