Patents by Inventor Takuya Honda

Takuya Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070088881
    Abstract: A serial communication circuit for performing full duplex serial communication with a microcomputer includes a counter and a timer. The counter is incremented by each pulse of a serial clock signal output from the microcomputer. When the counter reaches the number of bits of serial data output from the microcomputer, the counter outputs a load signal to a receiving register. The timer starts to count after the counter outputs the receiving load signal for the first time and continues to count during the serial communication. The timer expires at a predetermined time interval. Each time the timer expires, the timer outputs a timer signal. In response to the timer signal, a synchronous signal is output to the microcomputer, the counter is cleared to zero, and data to be output to the microcomputer is loaded into a sending register.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 19, 2007
    Applicant: DENSO CORPORATION
    Inventor: Takuya Honda
  • Patent number: 7062346
    Abstract: A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. In the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the chips on a wafer is controlled based on a chip identification information formed on a wafer. The method includes the step of editing the chip identification information such that the chip identification information for chips having the same fabrication processing steps and chips formed on the same wafer can be read out successively. The method also includes the step of carrying out each of the fabrication processing steps based on the chip identification information formed on the wafer by reading out the chip identification information.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: June 13, 2006
    Assignee: Fujitsu Limited
    Inventors: Osamu Takagi, Tsuneo Iizuka, Tetsurou Honda, Takuya Honda
  • Patent number: 7030803
    Abstract: The A/D converter has first and second PPDC circuits (pulse-phase-difference coding circuits). The first PPDC circuit performs A/D conversions on the reference voltage and on the voltage signal amplified by an amplifier in an alternating sequence, the amplifier using the reference voltage as a potential base thereof. The second PPDC circuit performs A/D conversions always on the reference voltage. The A/D-converted data set of the voltage signal outputted from the first PPDC circuit is corrected depending on the difference between the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the reference voltage and the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the voltage signal.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: April 18, 2006
    Assignee: Denso Corporation
    Inventors: Takuya Harada, Masakiyo Horie, Takuya Honda, Nobuyuki Tanaka
  • Publication number: 20060065720
    Abstract: A service execution device which includes a user identification information memory, an account identification information memory, a service execution section and an aggregation section. The user identification information memory stores user identification information for identifying users. The account identification information memory stores account identification information, which is associated with the user identification information and identifies accounts. The service execution section executes services in accordance with instructions from users for whom account identification information corresponding to user identification information is present and who are identified by this user identification information. The services are processes relating to document data. The aggregation section aggregates results of execution by the service execution section for each account of the account identification information.
    Type: Application
    Filed: March 9, 2005
    Publication date: March 30, 2006
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Takayuki Asako, Hitoshi Tsushima, Yasuyuki Shimizu, Kenji Tsutsumi, Takashi Hirata, Takuya Honda, Yukimasa Ishida, Hiroshi Yamamoto
  • Publication number: 20060066893
    Abstract: An instruction file execution device includes: a receiver that receives an instruction file that has a job flow described therein defining a cooperative linkage among jobs, and that instructs execution of predetermined processing of document data, and receives fee information and the document data when required; a determination section that determines whether any of the jobs being handled supplies information to a user based on the instruction file received by the receiver; a job execution section that executes the job being handled with respect to the document data received by the receiver; a fee calculator that adds fee information for the job being handled and fee information received by the receiver to derive new fee information; and a transmission section that transmits information, wherein when the determination section determines that the job being handled does not supply information to a user, the transmission section transmits, to an execution destination of any of the jobs subsequent to the job bein
    Type: Application
    Filed: March 9, 2005
    Publication date: March 30, 2006
    Applicant: Fuji Xerox Co., Ltd.
    Inventors: Yasuyuki Shimizu, Hitoshi Tsushima, Kenji Tsutsumi, Takashi Hirata, Takayuki Asako, Takuya Honda, Yukimasa Ishida, Hiroshi Yamamoto
  • Publication number: 20060070071
    Abstract: An instruction file execution device which includes a receiver, a comparison section and a job execution section. The receiver receives an instruction file and a usable money amount, which instruction file describes a job flow which defines linking of a number of jobs. The comparison section compares an execution charge of a job being handled of the jobs of the instruction file received by the receiver with the usable money amount received by the receiver. If the comparison section determines that the usable money amount is greater than or equal to the execution charge, the job execution section executes the job being handled.
    Type: Application
    Filed: March 15, 2005
    Publication date: March 30, 2006
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Yasuyuki Shimizu, Hitoshi Tsushima, Kenji Tsutsumi, Takashi Hirata, Takayuki Asako, Takuya Honda, Yukimasa Ishida, Hiroshi Yamamoto
  • Publication number: 20050285769
    Abstract: The A/D converter has first and second PPDC circuits (pulse-phase-difference coding circuits). The first PPDC circuit performs A/D conversions on the reference voltage and on the voltage signal amplified by an amplifier in an alternating sequence, the amplifier using the reference voltage as a potential base thereof. The second PPDC circuit performs A/D conversions always on the reference voltage. The A/D-converted data set of the voltage signal outputted from the first PPDC circuit is corrected depending on the difference between the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the reference voltage and the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the voltage signal.
    Type: Application
    Filed: February 8, 2005
    Publication date: December 29, 2005
    Inventors: Takuya Harada, Masakiyo Horie, Takuya Honda, Nobuyuki Tanaka
  • Publication number: 20050206939
    Abstract: A service processing device and service linking processing method which can execute appropriate tabulation for each of service linked processings which combine a plurality of services. It is judged whether or not individual instruction information, which is transmitted from a linking processing server, has been received, and operation stands-by until receipt. Each service processing device interprets service processing request contents described in the individual instruction information, and executes a service processing. When execution of the service processing is completed, a results log of the service processing is stored in the service processing device together with a request ID, a client ID, and billing destination information.
    Type: Application
    Filed: October 12, 2004
    Publication date: September 22, 2005
    Applicant: Fuji Xerox Co., Ltd.
    Inventors: Kenji Tsutsumi, Hitoshi Tsushima, Takashi Hirata, Takayuki Asako, Takuya Honda, Yukimasa Ishida, Hiroshi Yamamoto, Yasuyuki Shimizu
  • Patent number: 6862725
    Abstract: A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. One aspect of the present invention, there is provided the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially with a plurality of chips on a wafer based on a chip identification information formed on the wafer, the method comprises at least two steps sharing the chip identification information before at least one of the two steps is carried out, wherein the steps are not immediately neighbored with each other in fabrication processing sequence.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: March 1, 2005
    Assignee: Fujitsu Limited
    Inventors: Osamu Takagi, Tsuneo Iizuka, Tetsurou Honda, Takuya Honda
  • Publication number: 20040225385
    Abstract: A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. One aspect of the present invention, there is provided the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially with a plurality of chips on a wafer based on a chip identification information formed on the wafer, the method comprises at least two steps sharing the chip identification information before at least one of the two steps is carried out, wherein the steps are not immediately neighbored with each other in fabrication processing sequence.
    Type: Application
    Filed: June 2, 2004
    Publication date: November 11, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Osamu Takagi, Tsuneo Iizuka, Tetsurou Honda, Takuya Honda
  • Publication number: 20040053002
    Abstract: A multi-component floor mat that, in one embodiment, is comprised of a first base or frame portion, intended to be positioned on the floor, that is dimensioned to accommodate a second flexible textile mat or rug portion that is releasably held in place on or in said base or frame portion by a plurality of magnets associated with one or both portions, thereby allowing for the easy removal or replacement of the textile portion of the mat and the economical laundering of same. The pile surface of the mat component features one of a plurality of messages, printed in reactive dyes, intended to convey information to users of the mat.
    Type: Application
    Filed: June 12, 2003
    Publication date: March 18, 2004
    Inventors: Seiin Kobayashi, Mamiko Yamada, Takuya Honda
  • Publication number: 20040013848
    Abstract: The present mat system includes a plurality of mats intended to convey specific and needed information, in interior locations, to the end-user's customers or family. These mats are printed with words, letters, or symbols that convey the desired information. The information may be printed in any language or dialect, even incorporating slang or colloquial expressions. By using these mats, the end-users indicate their care and appreciation for their customers or family. In one embodiment, the mats include a textile upper surface (such as a pile surface) and a solid backing. Because the mats are printed with reactive dyes, they are more capable of withstanding vigorous laundering without causing dye transfer onto other mats.
    Type: Application
    Filed: June 12, 2003
    Publication date: January 22, 2004
    Inventors: Seiin Kobayashi, Mamiko Yamada, Takuya Honda
  • Publication number: 20020017708
    Abstract: A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. One aspect of the present invention, there is provided the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially with a plurality of chips on a wafer based on a chip identification information formed on the wafer, the method comprises at least two steps sharing the chip identification information before at least one of the two steps is carried out, wherein the steps are not immediately neighbored with each other in fabrication processing sequence.
    Type: Application
    Filed: September 20, 2001
    Publication date: February 14, 2002
    Applicant: Fujitsu Limited
    Inventors: Osamu Takagi, Tsuneo Iizuka, Tetsurou Honda, Takuya Honda
  • Patent number: 5190712
    Abstract: A method for melt-molding a water-soluble vinyl alcohol polymer which includes melt-molding a water-soluble oxyalkylene group-containing vinyl alcohol copolymer under substantially anhydrous conditions and substantially without use of plasticizer, the copolymer having a vinyl alcohol unit (A), a vinyl ester unit (B) and an oxyalkylene ether unit (C) of the formulas: ##STR1## wherein R.sup.1 is an alkyl group; R.sup.2 and R.sup.3 each is a hydrogen atom or an alkyl group; R.sup.4 is a hydrogen atom, an alkyl group, a phenyl group or a substituted phenyl group; n is equal to 1 through 50; in proportions of a mol %, b mol % and c mol %, respectively, where0.1.ltoreq.c.ltoreq.20,50.ltoreq.100a/(a+b).ltoreq.100,and the oxyalkylene moiety (CHR.sup.2 --CHR.sup.3 --O--).sub.n of unit (C) accounts for 3 to 40 percent by weight of the total resin, and having a melt index of not less than 5 g/10 min. under a load of 2160 at a temperature of 210.degree. C.
    Type: Grant
    Filed: August 30, 1991
    Date of Patent: March 2, 1993
    Assignee: Nippon Gohsei Kagaku Kogyo Kabushiki Kaisha
    Inventors: Tsukasa Oishi, Toru Seki, Takuya Honda