Abstract: An example method includes forming a gate electrode on an active region of a semiconductor substrate surrounded by a STI region; implanting a first dopant into the active region by using the gate electrode as a mask to form LDD regions; forming a liner film on top and side surfaces of the gate electrode, the STI region, and the LDD regions; forming a side wall spacer on the side surfaces of the gate electrode with the liner film interposed therebetween; implanting, with covering the STI region and the LDD regions by the liner film, a second dopant by using the gate electrode, the liner film formed on the side surfaces of the gate electrode, and the side wall spacer as a mask to form source/drain regions; and removing the side wall spacer.

Abstract: A semiconductor device includes a first transistor of a first conductivity type having a first gate insulating film and a first gate structure on the first gate insulating film, the first gate structure including a first conductive film, a second conductive film on the first conductive film and a third conductive film on the second conductive film; and a second transistor of the first conductivity type having a second gate insulating film and a second gate structure on the second gate insulating film, the second gate structure including a fourth conductive film and a fifth conductive film on the fourth conductive film; wherein the first gate insulating film and the second gate insulating film are the same, the second conductive film and the fourth conductive film are the same and the third conductive film and the fifth conductive film are the same.

Abstract: Disclosed herein is a method that includes forming a gate electrode on an active region of a semiconductor substrate surrounded by a STI region; implanting a first dopant into the active region by using the gate electrode as a mask to form LDD regions; forming a liner film on top and side surfaces of the gate electrode, the STI region, and the LDD regions; forming a side wall spacer on the side surfaces of the gate electrode with the liner film interposed therebetween; implanting, with covering the STI region and the LDD regions by the liner film, a second dopant by using the gate electrode, the liner film formed on the side surfaces of the gate electrode, and the side wall spacer as a mask to form source/drain regions; and removing the side wall spacer.

Abstract: Some embodiments include an integrated device having a first transistor gate over a first region of a semiconductor base, and having a second transistor gate over a second region of the semiconductor base. First sidewall spacers are along sidewalls of the first transistor gate. The first sidewall spacers include SiBNO, where the chemical formula lists primary constituents rather than a specific stoichiometry. The first sidewall spacers have a first thickness. Second sidewall spacers are along sidewalls of the second transistor gate. The second sidewall spacers have a second thickness which is less than the first thickness. First source/drain regions are within the semiconductor base and are operatively proximate the first transistor gate. Second source/drain regions are within the semiconductor base and are operatively proximate the second transistor gate. Some embodiments include methods of forming integrated devices.

Abstract: Some embodiments include a transistor having a gate, with the gate being over a semiconductor base. The gate has sidewalls. A channel region is under the gate. Spacers are along the sidewalk. The spacers each include a spacer structure and a void between the spacer structure and the gate. The spacer structures each include a vertical segment extending upwardly from a horizontal segment. The vertical segments join to the horizontal segments at corners. Source/drain regions are adjacent the channel region. The voids may be along the entirety of the vertical segments of the spacer structures, and may extend around the corners and to under the horizontal segments of the spacer structures. Additionally, or alternatively, bottoms of the voids may be adjacent fill material which includes silicon, nitrogen, boron and oxygen. Some embodiments include methods of forming transistors.

Abstract: Some embodiments include an integrated device having a first transistor gate over a first region of a semiconductor base, and having a second transistor gate over a second region of the semiconductor base. First sidewall spacers are along sidewalls of the first transistor gate. The first sidewall spacers include SiBNO, where the chemical formula lists primary constituents rather than a specific stoichiometry. The first sidewall spacers have a first thickness. Second sidewall spacers are along sidewalls of the second transistor gate. The second sidewall spacers have a second thickness which is less than the first thickness. First source/drain regions are within the semiconductor base and are operatively proximate the first transistor gate. Second source/drain regions are within the semiconductor base and are operatively proximate the second transistor gate. Some embodiments include methods of forming integrated devices.

Abstract: Some embodiments include a transistor having a gate, with the gate being over a semiconductor base. The gate has sidewalls. A channel region is under the gate. Spacers are along the sidewalk. The spacers each include a spacer structure and a void between the spacer structure and the gate. The spacer structures each include a vertical segment extending upwardly from a horizontal segment. The vertical segments join to the horizontal segments at corners. Source/drain regions are adjacent the channel region. The voids may be along the entirety of the vertical segments of the spacer structures, and may extend around the corners and to under the horizontal segments of the spacer structures. Additionally, or alternatively, bottoms of the voids may be adjacent fill material which includes silicon, nitrogen, boron and oxygen. Some embodiments include methods of forming transistors.

Abstract: Some embodiments include an integrated device having a first transistor gate over a first region of a semiconductor base, and having a second transistor gate over a second region of the semiconductor base. First sidewall spacers are along sidewalls of the first transistor gate. The first sidewall spacers include SiBNO, where the chemical formula lists primary constituents rather than a specific stoichiometry. The first sidewall spacers have a first thickness. Second sidewall spacers are along sidewalls of the second transistor gate. The second sidewall spacers have a second thickness which is less than the first thickness. First source/drain regions are within the semiconductor base and are operatively proximate the first transistor gate. Second source/drain regions are within the semiconductor base and are operatively proximate the second transistor gate. Some embodiments include methods of forming integrated devices.

Abstract: Some embodiments include an integrated assembly having a first transistor adjacent to a second transistor. The first transistor has a first conductive gate material over a first insulative region, and the second transistor has a second conductive gate material over a second insulative region. A continuous high-k dielectric film extends across both of the first and second insulative regions. In some embodiments, the transistors may be incorporated into a sense amplifier.

Abstract: Some embodiments include an integrated assembly having a first transistor adjacent to a second transistor. The first transistor has a first conductive gate material over a first insulative region, and the second transistor has a second conductive gate material over a second insulative region. A continuous high-k dielectric film extends across both of the first and second insulative regions. In some embodiments, the transistors may be incorporated into a sense amplifier.

Abstract: Some embodiments include an integrated assembly having a first transistor adjacent to a second transistor. The first transistor has a first conductive gate material over a first insulative region, and the second transistor has a second conductive gate material over a second insulative region. A continuous high-k dielectric film extends across both of the first and second insulative regions. In some embodiments, the transistors may be incorporated into a sense amplifier.