Abstract: A cache memory device includes: a processor; and a main memory and a cache memory coupled to the processer, wherein the processor executes a process includes: obtaining a first address in the main memory; obtaining a first index that indicates a first cache index of the cache memory by a hash function; storing a first tag of the first address in the first cache index; generating a second address, a second tag; obtaining by the hash function a second index that indicates a second cache index of the cache memory; changing the second index so that the second index and the first index match and storing the second tag with a third index that is indicated by the changed second index in the cache memory and in a way that is different from the way in which the tag of the first address is stored.

Abstract: A static RAM is disclosed wherein a combination logic circuit can operate at a higher speed to improve the throughput and the load such as the number of gates and/or wiring lines connected to a data output line can be reduced. The static RAM comprises a RAM cell for storing data, a differential amplifier for amplifying a signal read out from the RAM cell, a level keeping circuit for keeping a level of a signal outputted from the differential amplifier, a first output line for outputting an output signal of a kept level from the level keeping circuit upon reading accessing to the static RAM as a static output, and a second output line for outputting a state of at least one of a positive phase bit line and an inverted phase bit line of the differential amplifier upon reading accessing to the static RAM as a dynamic output. The static RAM can be suitably used with an associative storage circuit represented by a tag RAM circuit of a cache memory system and like storage circuits.