Patents by Inventor Takuya Masaki

Takuya Masaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11003509
    Abstract: A lock control apparatus includes one or more memories, and one or more processors configured to perform setting of, as a target node, each of one or more child nodes other than eldest child nodes among child nodes relating to parent nodes in each of layers of data structure formed by a tree structure, when a first process for first data associated with a first node in the data structure proceeds in a direction from a parent node to a child node, perform determination of whether the first node is the target node, and perform lock of the first node when the first node is the target node.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 11, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Takuya Masaki, Kiichi Yamada, Masahiko Nagata, Yoshihiro Yasuoka, Hisashi Sugawara
  • Publication number: 20190163542
    Abstract: A lock control apparatus includes one or more memories, and one or more processors configured to perform setting of, as a target node, each of one or more child nodes other than eldest child nodes among child nodes relating to parent nodes in each of layers of data structure formed by a tree structure, when a first process for first data associated with a first node in the data structure proceeds in a direction from a parent node to a child node, perform determination of whether the first node is the target node, and perform lock of the first node when the first node is the target node.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 30, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Takuya Masaki, Kiichi YAMADA, Masahiko Nagata, Yoshihiro Yasuoka, Hisashi Sugawara
  • Patent number: 10018955
    Abstract: A half bridge circuit of a class-D amplifier outputs a voltage in accordance with switching of a first switching element and of a second switching element, to a load. A high side gate drive circuit and a low side gate drive circuit respectively drive the first and second switching elements. A bootstrap capacitor connected between the high side gate drive circuit and an output terminal of the half bridge circuit is charged by a charging current from a second direct-current power supply while the first switching element is off. An inductance component for noise suppression, and a voltage limit element that is connected in parallel with the inductance component and is for limiting a voltage that occurs at the inductance component, are provided on a path in which the charging current flows.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: July 10, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takuya Masaki
  • Publication number: 20170277108
    Abstract: A half bridge circuit of a class-D amplifier outputs a voltage in accordance with switching of a first switching element and of a second switching element, to a load. A high side gate drive circuit and a low side gate drive circuit respectively drive the first and second switching elements. A bootstrap capacitor connected between the high side gate drive circuit and an output terminal of the half bridge circuit is charged by a charging current from a second direct-current power supply while the first switching element is off. An inductance component for noise suppression, and a voltage limit element that is connected in parallel with the inductance component and is for limiting a voltage that occurs at the inductance component are provided on a path in which the charging current flows.
    Type: Application
    Filed: March 16, 2017
    Publication date: September 28, 2017
    Inventor: Takuya Masaki