Patents by Inventor Takuya Matsushita

Takuya Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079689
    Abstract: To provide a laminate type solid-state battery capable of preferably accommodating an electrode laminate. A laminate type solid-state battery comprising: an electrode laminate; and a casing body being formed of a laminate film and accommodating the electrode laminate, the casing body comprising an insulating member in an interior thereof, the insulating member abutting at least one of laminate end surfaces of the electrode laminate, the insulating member having an inclined surface that outwardly inclines from the electrode laminate in a cross-sectional view along the laminate direction, the inclined surface and the laminate surface of the electrode laminate forming an angle greater than 90° and less than 180°.
    Type: Application
    Filed: July 24, 2023
    Publication date: March 7, 2024
    Inventors: Takuya TANIUCHI, Tadashi MATSUSHITA, Toshiyuki ARIGA
  • Publication number: 20120083983
    Abstract: To provide a vehicular braking control device which, at the time of a collision of a host vehicle, can apply a braking force to the host vehicle while reducing the potential for a rear-end collision from a following vehicle.
    Type: Application
    Filed: February 19, 2010
    Publication date: April 5, 2012
    Applicant: BOSCH CORPORATION
    Inventors: Christian Danz, Takuya Matsushita
  • Patent number: 6617080
    Abstract: The present invention provides a photomask, a semiconductor device, and a method for exposing through the photomask. The photomask comprises a photomask substrate, and an on-mask circuit area including an on-mask circuit pattern and an on-mask test mark area including an on-mask test pattern, both formed on the surface of the substrate, wherein the photomask substrate further includes an on-mask photolithography screening mark area including an on-mask comparison pattern and an on-mask screening pattern, the on-mask comparison pattern has substantially the same configuration as at least a part of the on-mask circuit pattern, and the on-mask screening pattern has substantially the same configuration as at least a part of the on-mask test pattern. The present invention allows it to measure the actual displacement generated from an overlaying (i.e. alignment) process for the purpose of eliminating of an the overlay displacement which can take place in a photolithography process.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: September 9, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihide Kawachi, Takuya Matsushita, Shigenori Yamashita, Yuki Miyamoto, Atsushi Ueno, Shinroku Maejima
  • Patent number: 6514122
    Abstract: A product pattern and a test pattern for managing a focus offset value are patterned onto a product wafer by means of exposure, and is patterned onto the product wafer by means of exposure. The exposed product wafer is developed. A measurement section measures the dimension of the test pattern patterned on the product wafer. On the basis of the thus-measured dimension of the test pattern, the focus off set value set in a system for manufacturing a semiconductor device is computed by a computation section. The focus offset value set in a projection optical system of the system for manufacturing a semiconductor device is adjusted by means of an adjustment section so as to become identical with the computed focus offset value.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: February 4, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takayuki Saito, Tadashi Miyagi, Takuya Matsushita
  • Publication number: 20020048857
    Abstract: A product pattern and a test pattern for managing a focus offset value are patterned onto a product wafer by means of exposure, and is patterned onto the product wafer by means of exposure The exposed product wafer is developed. A measurement section measures the dimension of the test pattern patterned on the product wafer. On the basis of the thus-measured dimension of the test pattern, the focus offset value set in a system for manufacturing a semiconductor device is computed by a computation section. The focus offset value set in a projection optical system of the system for manufacturing a semiconductor device is adjusted by means of an adjustment section so as to become identical with the computed focus offset value.
    Type: Application
    Filed: February 2, 2001
    Publication date: April 25, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Takayuki Saito, Tadashi Miyagi, Takuya Matsushita