Abstract: According to one embodiment, a semiconductor memory device includes: a stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and a stepped portion in which the plurality of conductive layers is processed in a stepped shape; and a plurality of second pillars that extends in the stacked body in the stepped portion, in which each of the plurality of second pillars includes a second insulating layer extending in the stacked body in the stacking direction, a semiconductor layer covering a side wall of the second insulating layer, a third insulating layer disposed in contact with a side wall of the semiconductor layer and covering the side wall of the semiconductor layer, and a fourth insulating layer disposed in contact with a side wall of the third insulating layer and covering the side wall of the third insulating layer.

Abstract: A semiconductor memory device according to an embodiment includes a first conductor, first to third insulators, a second conductor, and a memory pillar. The first conductor and the first insulator are arranged in a first direction. The second conductor extends in the first direction to penetrate the first conductor and the first insulator. The memory pillar extends in the first direction to penetrate the first conductor and the first insulator, and includes a semiconductor. The second insulator is provided between the first conductor and the second conductor. The third insulator includes a first portion between the second insulator and the first conductor, a portion on a surface on one side of the second insulator in the first direction, and a portion on a surface on the other side of the second insulator in the first direction. The third insulator offers an etching rate smaller than the second insulator.

Abstract: A semiconductor memory device includes finger structures arranged in a first direction and an inter-finger insulating member disposed between a first finger structure and a second finger structure. The first finger structure includes conductive layers stacked in a stacking direction, a semiconductor column opposed to the conductive layers, a first insulating layer and a second insulating layer covering terrace portions of the conductive layers, and a third insulating layer disposed between the first insulating layer and the inter-finger insulating member in the first direction. The second insulating layer and the third insulating layer have mutually same main components. At least a part of a main component of the first insulating layer is different from the main components of the second insulating layer and the third insulating layer. The second insulating layer and the third insulating layer have mutually different etching rates.

Abstract: According to one embodiment, a semiconductor device includes a stacked film with first insulating films and electrode layers alternately stacked in a first direction. The device further includes a columnar portion extending in the first direction and provided in a first region of the stacked film. The columnar portion forms memory cells at its intersections with the electrode layers. The device further includes a support column portion provided in a second region and extending in the first direction. A conductive plug is provided on a first electrode layer among the electrode layers in the second region. A first side surface of the support column portion faces a second side surface of the plug and the second side surface is concave in a direction toward the first side surface.

Abstract: A semiconductor memory device includes stacked conductive layers, a first insulating layer above the conductive layers in a stacking direction, and a second insulating layer above the first insulating layer and the conductive layers. A first semiconductor pillar extends in the stacking direction through the conductive layers and the first insulating layer. A first charge storage film is between the conductive layers and the first semiconductor pillar. A via contact electrode extends in the stacking direction through the second insulating layer and is connected to a first end of the first semiconductor pillar. The first insulating layer comprises a material different from that of the second insulating layer.

Abstract: A blood pressure monitoring apparatus including a linear relationship storage portion storing previously stored linear relationships, a blood pressure measurement portion measuring a real arterial pressure of the person to be measured, a proper relationship generation portion applying, for the person to be measured, the real arterial pressure, real compression pressures, and real pulse wave propagation velocities, to thereby generate a proper relationship on the person to be measured among the real arterial pressures of the person to be measured, the real compression pressures, and the real pulse wave propagation velocities, and a blood pressure estimation portion applying, for the person to be measured, the real compression pressures and the real pulse wave propagation velocities obtained under the real compression pressures, to the proper relationship on the person to be measured, to thereby estimate the estimated arterial pressure.

Abstract: According to one embodiment, a semiconductor storage device includes a stacked body with conductive layers which are spaced apart one from another along a first direction. A pillar structure extends in the first direction through the conductive layers and has protruding parts, each of which protrudes outwardly from the pillar structure towards a conductive layer. The pillar structure includes a semiconductor layer, a tunnel insulating layers separately in each of the protruding parts between the semiconductor layer and the conductive layer. There is no tunnel insulating layer in the region between the adjacent protruding parts in the first direction. A charge storage layer is also separately in each protruding part between the tunnel insulating layer and the conductive layer.

Abstract: According to one embodiment, a semiconductor memory device includes: a first stacked body that includes a memory region, a stepped region, and a connection region arranged in a first direction; a plurality of first pillars that is disposed in the memory region, extends in the first stacked body in the stacking direction; a plurality of second pillars that includes a second insulating layer, has a layer structure different from a layer structure of the first pillars, and extends in the stacking direction in a position overlapping a stepped portion disposed in the stepped region in the stacking direction; and a plurality of third pillars that extends in the first stacked body in the stacking direction, and has a same layer structure as the layer structure of the first pillars, at least a part of the plurality of third pillars being disposed in the connection region.

Abstract: According to one embodiment, a semiconductor memory device includes: a stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and a stepped portion in which the plurality of conductive layers is processed in a stepped shape; and a plurality of second pillars that extends in the stacked body in the stepped portion, in which each of the plurality of second pillars includes a second insulating layer extending in the stacked body in the stacking direction, a semiconductor layer covering a side wall of the second insulating layer, a third insulating layer disposed in contact with a side wall of the semiconductor layer and covering the side wall of the semiconductor layer, and a fourth insulating layer disposed in contact with a side wall of the third insulating layer and covering the side wall of the third insulating layer.

Abstract: A semiconductor memory device includes multiple first electrode layers stacked in a first direction, multiple second electrode layers stacked in the first direction, a first columnar body extending through the multiple first electrode layers in the first direction, a second columnar body extending through the multiple second electrode layers in the first direction, a connection part connecting the first columnar body and the second columnar body, and a spacer film having an island configuration surrounding the connection part. The multiple first electrode layers and the multiple second electrode layers are arranged in the first direction, and the connection part and the spacer film are provided between the multiple first electrode layers and the multiple second electrode layers.

Abstract: A mask material for plasma dicing, which is used in a plasma step, whose surface roughness Rz at the surface side that does not touch with an adherend is from 0.1 ?m to 1.5 ?m; a mask-integrated surface protective tape; and a method of producing a semiconductor chip.

Abstract: According to one embodiment, a semiconductor memory device includes a pair of first plate-shaped portions that extends in a stacking direction of respective layers of a first stacked body and a first direction crossing the stacking direction, and is in contact with a second stacked body on both sides of the second stacked body in a second direction crossing the stacking direction and the first direction, a pair of second plate-shaped portions of which longitudinal direction is in the first direction, the pair of second plate-shaped portions extending through the first stacked body in the stacking direction on both sides of the pair of first plate-shaped portions in the second direction in positions apart from the pair of first plate-shaped portions, and a columnar portion that extends through the first stacked body in the stacking direction in a position between one of the first plate-shaped portions out of the pair of first plate-shaped portions and one of the second plate-shaped portions, that faces the one

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first members, first conductive layers, and first and second pillars. The substrate includes first and second areas, and block areas. The first conductive layers are split by the first members. The first pillars are provided in an area in which the first area and the block areas overlap. The second pillars are provided in an area in which the second area and the block areas overlap. The second area includes a first sub-area in which the second pillars are periodically arranged in an area that overlaps at least one block area in the block areas. In the first sub-area, at least one second pillar is omitted from the second pillars that are periodically arranged.

Abstract: A semiconductor storage device in an embodiment includes a stacked body including a plurality of conductive layers stacked with an insulating layer interposed therebetween, end portions of the plurality of conductive layers being arranged like stairs in a stair portion, a plurality of memory cells each disposed in a crossing portion of at least a part of the plurality of conductive layers and a pillar extending in a stacking direction of the plurality of conductive layers in the stacked body, a first structure having a longitudinal direction in a first direction crossing the stacking direction and dividing the stacked body, and a second structure disposed in the stair portion, extending in a second direction toward the first structure, extending in the stacking direction in the stacked body, and having a width wider at a first portion farther from the first structure than at a second portion closer to the first structure.

Abstract: A semiconductor memory device includes multiple first electrode layers stacked in a first direction, multiple second electrode layers stacked in the first direction, a first columnar body extending through the multiple first electrode layers in the first direction, a second columnar body extending through the multiple second electrode layers in the first direction, a connection part connecting the first columnar body and the second columnar body, and a spacer film having an island configuration surrounding the connection part. The multiple first electrode layers and the multiple second electrode layers are arranged in the first direction, and the connection part and the spacer film are provided between the multiple first electrode layers and the multiple second electrode layers.

Abstract: A semiconductor memory device according to an embodiment includes first and second conductive layers, and a pillar. The pillar is penetrating the first conductive layers and the second semiconductor layers. The pillar includes first and second semiconductor layers, a third conductive layer, and a gate insulating film. The first semiconductor layer is facing the first conductive layers. The second semiconductor layer is facing the second conductive layers. The third conductive layer is provided between the second semiconductor layer and the second conductive layers. The gate insulating film is provided between the second semiconductor layer and the third conductive layer. The third conductive layer is electrically coupled to the second conductive layers.

Abstract: A mask material for plasma dicing, which is used in a plasma step, whose surface roughness Rz at the surface side that does not touch with an adherend is from 0.1 ?m to 1.5 ?m; a mask-integrated surface protective tape; and a method of producing a semiconductor chip.