Abstract: The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region, two impurity diffusion drift layers formed on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region in the surface of the high-withstand voltage active region under the polysilicon layers, and a gate electrode formed through a gate oxide film on bottom and side surfaces of the trench portion and end surfaces and upper surfaces of adjacent regions of the polysilicon layers close to the trench portion, and source and drain regions are formed in the two polysilicon layers excluding the adjacent regions covered with the gate electrode.

Abstract: In the case where a variable resistive element, which is made of a variable resistor provided between a first and second electrodes, and of which the electrical resistance varies by applying a voltage pulse between the two electrodes, is applied to a resistance nonvolatile memory, there is a range of the resistance value of the variable resistive element in a low resistance state where the nonvolatile memory can operate normally. In the conventional manufacturing method the resistance value of the variable resistive element is too low, therefore, it can not be controlled within a desired range of the resistance value. A step of carrying out of a reduction process is provided at any point after the step of forming a variable resistor material as a film, it has thereby become possible to increase the resistance value of the variable resistive element, which is too low in the conventional method.

Abstract: A semiconductor memory device comprising a variable resistance element having a variable resistor between a first electrode and a second electrode, in which electric resistance is changed by applying a voltage pulse between the electrodes comprises at least one reaction preventing film made of a material having an action of blocking the permeation of a reduction species promoting a reduction reaction of the variable resistor and an oxidation species promoting an oxidation reaction of the variable resistor. This prevents the resistance value of the variable resistance element from fluctuating due to a reduction reaction or an oxidation reaction of the variable resistor caused by hydrogen or oxygen existing in the manufacturing steps, so that a semiconductor memory device having a small variation of the resistance value and having a good controllability can be realized with good repeatability.

Abstract: The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region, two impurity diffusion drift layers formed on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region in the surface of the high-withstand voltage active region under the polysilicon layers, and a gate electrode formed through a gate oxide film on bottom and side surfaces of the trench portion and end surfaces and upper surfaces of adjacent regions of the polysilicon layers close to the trench portion, and source and drain regions are formed in the two polysilicon layers excluding the adjacent regions covered with the gate electrode.

Abstract: A semiconductor device fabrication method comprises (1) forming a patterned mask layer on an oxide layer of a Mn-containing perovskite type oxide; (2) heat-treating the oxide layer; and (3) patterning the oxide layer with an etching solution containing at least one of hydrochloric acid, sulfuric acid, and nitric acid after the heat treatment of the oxide layer.

Abstract: In the case where a variable resistive element, which is made of a variable resistor provided between a first and second electrodes, and of which the electrical resistance varies by applying a voltage pulse between the two electrodes, is applied to a resistance nonvolatile memory, there is a range of the resistance value of the variable resistive element in a low resistance state where the nonvolatile memory can operate normally. In the conventional manufacturing method the resistance value of the variable resistive element is too low, therefore, it can not be controlled within a desired range of the resistance value. A step of carrying out of a reduction process is provided at any point after the step of forming a variable resistor material as a film, it has thereby become possible to increase the resistance value of the variable resistive element, which is too low in the conventional method.

Abstract: A semiconductor device fabrication method comprises (1) forming a patterned mask layer on an oxide layer of a Mn-containing perovskite type oxide; (2) heat-treating the oxide layer; and (3) patterning the oxide layer with an etching solution containing at least one of hydrochloric acid, sulfuric acid, and nitric acid after the heat treatment of the oxide layer.

Abstract: On a silicon substrate 201, there are formed a silicon oxide 202, an adhesion layer 203 consisting of TiO2, a lower electrode 204 consisting of Pt, a ferroelectric thin film 205, and an upper electrode 206 consisting of Pt. A portion of the ferroelectric thin film adjacent to the upper electrode 206 is formed from a compound with a composition formula of SrBi2 (TaxNb1-x)2O9 where x=0.7. A compound with a value x in the composition formula being greater than 0.7 is used for the portion of the ferroelectric thin film adjacent to the upper electrode 206, so as to generate an appropriate number of grain boundaries on the surface of the ferroelectric film 205, the grain boundaries enabling implementation of anchoring effect between the ferroelectric film 205 and the upper electrode 206, thereby achieving prevention of exfoliation of the upper electrode 206 from the ferroelectric film 205.

Abstract: On a silicon substrate 201, there are formed a silicon oxide 202, an adhesion layer 203 consisting of TiO2, a lower electrode 204 consisting of Pt, a ferroelectric thin film 205, and an upper electrode 206 consisting of Pt. A portion of the ferroelectric thin film adjacent to the upper electrode 206 is formed from a compound with a composition formula of SrBi2(TaxNb1-x)2O9 where x=0.7. A compound with a value x in the composition formula being greater than 0.7 is used for the portion of the ferroelectric thin film adjacent to the upper electrode 206, so as to generate an appropriate number of grain boundaries on the surface of the ferroelectric film 205, the grain boundaries enabling implementation of anchoring effect between the ferroelectric film 205 and the upper electrode 206, thereby achieving prevention of exfoliation of the upper electrode 206 from the ferroelectric film 205.