Abstract: An electronic device comprises: a transmission antenna configured to transmit transmission waves; a reception antenna configured to receive reflected waves resulting from reflection of the transmission waves; and a controller. The controller is configured to detect an object reflecting the transmission waves, based on a transmission signal transmitted as the transmission waves and a reception signal received as the reflected waves. The controller is configured to make a range of detection of the object by the transmission signal and the reception signal, variable.

Abstract: An object tracking device that can track an object accurately and consistently is provided. An object tracking device (20) includes an input interface (21), a processor (23), and an output interface (24). The input interface (21) is configured to acquire sensor data. The processor (23) is configured to detect a detection target from the sensor data and track the detection target using Kalman filters associated with each of the detection target and an observed value. The output interface (24) is configured to output a detection result regarding the detection target. The processor (23) is configured to impose a limit on a range of variation in an index of the Kalman filters that influences tracking of the detection target.

Abstract: An electronic device includes a transmission antenna that transmits a transmission wave, a reception antenna that receives a reflected wave that is the reflected transmission wave, and a control unit that detects an object that reflects the transmission wave, based on a transmission signal transmitted as the transmission wave and a reception signal received as the reflected wave. The electronic device transmits, to an information processing apparatus, sensing information based on the transmission signal and the reception signal at a location of the electronic device along with location information of the electronic device.

Abstract: An audio signal processor includes a difference detecting circuit, a gain switching circuit, a differential gain value changing circuit, and a gain control circuit. The difference detecting circuit detects a differential gain value being a first total gain value being a gain value to be switched and a second total gain value being the gain value that has been switched. The gain switching circuit switches the first total gain value to the second total gain value. The differential gain value changing circuit decreases the differential gain value as time passes. The gain control circuit corrects an inputted signal with the differential gain value that decreases as time passes.

Abstract: An audio signal processor includes a difference detecting circuit, a gain switching circuit, a differential gain value changing circuit, and a gain control circuit. The difference detecting circuit detects a differential gain value being a first total gain value being a gain value to be switched and a second total gain value being the gain value that has been switched. The gain switching circuit switches the first total gain value to the second total gain value. The differential gain value changing circuit decreases the differential gain value as time passes. The gain control circuit corrects an inputted signal with the differential gain value that decreases as time passes.

Abstract: A PLL circuit that operates in synchronization with an operating clock and generates and outputs a generated clock in synchronization with an external clock, including a multi-phase clock generating unit that generates multi-phase clocks including n clocks which have a same frequency and differ in phase one another, one of the clocks in the multi-phase clock being the operating clock, a frequency signal generating unit that outputs a frequency signal based on a phase difference signal from a phase comparator, an oscillating unit that generates and outputs a clock oscillating with a frequency corresponding to the frequency signal, and the phase comparator that measures a time difference between rising times or falling times of the inputted external clock and the oscillating unit based on the n clocks in the multi-phase clocks, and outputs a phase difference signal indicating the time difference based on a result of the measurement.

Abstract: A PLL circuit generating a generated clock in synchronization with an external clock by a phase locked loop includes a first detector for detecting whether or not the generated clock is in synchronization with the external clock, and a measuring device for measuring at least one of a high time from a rise to a fall of the external clock and a low time from a fall to a rise thereof. In a state that the generated clock and the external clock are in synchronization, when it is detected that a fluctuation of the high time or the low time becomes equal to or more than a predetermined value, the PLL circuit fixes a frequency of the generated clock to a frequency outputted at this time point, and continues output of the generated clock having the fixed frequency.

Abstract: A PLL circuit that operates in synchronization with an operating clock and generates and outputs a generated clock in synchronization with an external clock, including a multi-phase clock generating unit that generates multi-phase clocks including n clocks which have a same frequency and differ in phase one another, one of the clocks in the multi-phase clock being the operating clock, a frequency signal generating unit that outputs a frequency signal based on a phase difference signal from a phase comparator, an oscillating unit that generates and outputs a clock oscillating with a frequency corresponding to the frequency signal, and the phase comparator that measures a time difference between rising times or falling times of the inputted external clock and the oscillating unit based on the n clocks in the multi-phase clocks, and outputs a phase difference signal indicating the time difference based on a result of the measurement.

Abstract: A PLL circuit generating a generated clock in synchronization with an external clock by a phase locked loop includes a first detector for detecting whether or not the generated clock is in synchronization with the external clock, and a measuring device for measuring at least one of a high time from a rise to a fall of the external clock and a low time from a fall to a rise thereof. In a state that the generated clock and the external clock are in synchronization, when it is detected that a fluctuation of the high time or the low time becomes equal to or more than a predetermined value, the PLL circuit fixes a frequency of the generated clock to a frequency outputted at this time point, and continues output of the generated clock having the fixed frequency.