Patents by Inventor Takuya Shimano

Takuya Shimano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240099021
    Abstract: According to one embodiment, a magnetic memory device includes a lower insulating layer, first and second conductive portions provided in the lower insulating layer, first and second memory cells provided on the lower insulating layer and on the respective first and second conductive portions, and each including a magnetoresistance effect element, a switching element and a bottom electrode connected to corresponding one of the first and second conductive portions. As viewed from a third direction, a width of each of the first and second conductive portions is less than a width of a corresponding bottom electrode. The lower insulating layer has a void under a region between the first and second memory cells.
    Type: Application
    Filed: September 12, 2023
    Publication date: March 21, 2024
    Applicant: Kioxia Corporation
    Inventors: Naoki AKIYAMA, Kenichi YOSHINO, Kazuya SAWADA, Hyungjun CHO, Takuya SHIMANO
  • Publication number: 20240099158
    Abstract: According to one embodiment, a magnetic memory device includes a first wiring line extending in a first direction, a second wiring line provided on an upper layer side of the first wiring line and extending in a second direction intersecting the first direction, and a memory cell provided between the first wiring line and the second wiring line and including a magnetoresistance effect element and a switching element which are stacked in a third direction intersecting the first direction and the second direction. The first wiring line includes a first conductive layer and a second conductive layer provided on the first conductive layer and formed of a material containing carbon (C).
    Type: Application
    Filed: September 13, 2023
    Publication date: March 21, 2024
    Applicant: Kioxia Corporation
    Inventors: Kenichi YOSHINO, Tadaaki OIKAWA, Kazuya SAWADA, Naoki AKIYAMA, Takuya SHIMANO, Hyungjun CHO
  • Publication number: 20240099156
    Abstract: According to one embodiment, a magnetic memory device includes an electrode, and a magnetoresistance effect element provided on the electrode. The electrode includes a first electrode portion and a second electrode portion provided between the magnetoresistance effect element and the first electrode portion and containing a metal element selected from molybdenum (Mo) and ruthenium (Ru).
    Type: Application
    Filed: September 14, 2023
    Publication date: March 21, 2024
    Applicant: Kioxia Corporation
    Inventors: Kazuya SAWADA, Toshihiko NAGASE, Kenichi YOSHINO, Hyungjun CHO, Naoki AKIYAMA, Takuya SHIMANO, Tadaaki OIKAWA
  • Publication number: 20230301116
    Abstract: According to one embodiment, a magnetic: memory device includes a stacked structure in which a magnetoresistance effect element and a switching element are stacked. The switching element is provided on a lower layer side of the magnetoresistance effect element, and when viewed in a stacking direction of the magnetoresistance effect element and the switching element, a pattern of the switching element is located inside a pattern of the magnetoresistance effect element.
    Type: Application
    Filed: September 12, 2022
    Publication date: September 21, 2023
    Applicants: Kioxia Corporation, SK hynix Inc.
    Inventors: Kenichi YOSHINO, Kazuya SAWADA, Naoki AKIYAMA, Takuya SHIMANO, Cha Deok DONG, Keorock CHOI, Bokyung JUNG, Gukcheon KIM
  • Publication number: 20230292529
    Abstract: According to one embodiment, a magnetic memory device includes a plurality of memory cells each including a magnetoresistance effect element and a switching element provided on a lower layer side of the magnetoresistance effect element and connected in series to the magnetoresistance effect element. The switching element includes a bottom electrode, a top electrode and a switching material layer provided between the bottom electrode and the top electrode, and the top electrode includes a first portion formed of a first material and a second portion provided on a lower layer side of the first portion and formed of a second material different from the first material.
    Type: Application
    Filed: September 12, 2022
    Publication date: September 14, 2023
    Applicant: Kioxia Corporation
    Inventors: Naoki AKIYAMA, Kenichi YOSHINO, Kazuya SAWADA, Hyungjun CHO, Takuya SHIMANO
  • Publication number: 20230269950
    Abstract: A magnetic memory device according to an embodiment includes a first ferromagnetic layer, a first nonmagnetic layer on the first ferromagnetic layer, a second ferromagnetic layer on the first nonmagnetic layer, an oxide layer on the second ferromagnetic layer, and a second nonmagnetic layer on the oxide layer. The oxide layer contains an oxide of a rare-earth element. The second nonmagnetic layer contains cobalt (Co), iron (Fe), boron (B), and molybdenum (Mo).
    Type: Application
    Filed: June 16, 2022
    Publication date: August 24, 2023
    Applicant: Kioxia Corporation
    Inventors: Tadaaki OIKAWA, Kenichi YOSHINO, Kazuya SAWADA, Takuya SHIMANO, Young Min EEH, Taiga ISODA
  • Publication number: 20230071013
    Abstract: A magnetoresistance memory device includes a first conductor, a first insulator covering a side surface of the first conductor, a second conductor on the first conductor that are substantially made of a non-magnetic non-nitrogen material. The device includes a variable resistance material, a third conductor, a first ferromagnetic layer, an insulating layer, and a second ferromagnetic layer. The third conductor, a fourth conductor on the second ferromagnetic layer, and a second insulator covering side surfaces of the first and second ferromagnetic layers and insulating layer are substantially made of a non-nitrogen material. A third insulator is on the second insulator.
    Type: Application
    Filed: March 10, 2022
    Publication date: March 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Kazuya SAWADA, Toshihiko NAGASE, Kenichi YOSHINO, Kazuhiro TOMIOKA, Naoki AKIYAMA, Takuya SHIMANO, Hisanori AIKAWA, Taichi IGARASHI
  • Patent number: 5920082
    Abstract: An aperture rate of an active matrix substrate using TFTs can be improved, a short circuit can be prevent from being caused between a pixel electrode and a signal line, or a display defectiveness due to a coupling capacitor can be prevented, and display definition can be improved. A pixel electrode patterned by a back surface exposure technique is formed on a different surface by the presence of an insulating protection film. A source electrode and the pixel electrode are connected to each other by a first contact electrode formed of a transparent conductive film to be connected to a first contact hole formed through the insulating protection film. Since a connecting portion between the source electrode and the pixel electrode through the contact hole and a connecting portion between the pixel electrode and an auxiliary capacitor electrode are transparent conductive films, an aperture rate is not reduced.
    Type: Grant
    Filed: October 11, 1996
    Date of Patent: July 6, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Kitazawa, Tetsuya Iizuka, Takuya Shimano
  • Patent number: 5614731
    Abstract: A thin-film semiconductor element provided on a channel area with a channel protection layer, characterized by the fact that a source electrode layer and a drain electrode layer respectively have overlapping areas on the channel protection layer, the side walls of the source electrode layer and the drain electrode layer extend in the overlapping areas beyond the side wall of the channel protection layer in at least one direction of the width thereof, and the source electrode layer and the drain electrode layer possess points of overlap intersection with the semiconductor layer at the points of overlap intersection thereof with the channel protection layer. Owing to the construction described above, the leakage current generated by exposure to light can be decreased and the thin-film semiconductor element can be produced by a simple process of manufacture.
    Type: Grant
    Filed: August 11, 1995
    Date of Patent: March 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Uchikoga, Nobuki Ibaraki, Kouji Suzuki, Takuya Shimano, Kaichi Fukuda