Patents by Inventor Takuya Sunada
Takuya Sunada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9653240Abstract: A circuit breaker 1 comprises: a fixed-contact piece 2 with a fixed contact 21; a movable-contact piece 4 with a movable contact 41; a thermal actuator element 5 thermally transformable to move the movable-contact piece; a PTC thermistor 6 for conducting electricity between the movable-contact piece 4 and the fixed-contact piece 2; a main body 71 of a package provided with a holding recess 73 housing the above-mentioned components; and a cover 81 hermetically covering the holding recess 73. The fixed-contact piece 2 is embedded between an internal wall 74 and an external wall 75 of the main body 71. The PTC thermistor 6 is housed in an opened hollow 73d. In a planar view of the circuit breaker, a through-hole 76 penetrating through the external wall 75 overlaps with the opened hollow 73d, but does not overlap with the centroid O of the opened hollow 73d.Type: GrantFiled: July 29, 2015Date of Patent: May 16, 2017Assignee: KOMATSULITE MFG. CO., LTD.Inventors: Masashi Namikawa, Takuya Sunada
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Publication number: 20170040823Abstract: A driver circuit includes an input circuit, a control circuit, and an isolation circuit. The input circuit is configured to generate output signals corresponding to the input signals entered to a pair of input terminals. The input circuit includes an active element configured to driven by the input signals, and a capacitive element electrically connected between the active element and one of the input terminals. The control circuit is configured to send control signals corresponding to the output signals of the input circuit to the output circuit. The isolation circuit includes a plurality of capacitors electrically connected between the input circuit and the control circuit so as to provide electrical isolation between the input circuit and the control circuit.Type: ApplicationFiled: July 15, 2016Publication date: February 9, 2017Inventors: TAKUYA SUNADA, YASUSHI KONISHI, YU BUNGI
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Publication number: 20160226486Abstract: A semiconductor device includes an input circuit, an output circuit, an insulation circuit, and a semiconductor substrate. The insulation circuit includes at least one capacitor for electrically insulating the input circuit and the output circuit from each other. The at least one capacitor has two electrodes, one of which being electrically connected to the input circuit, and the other of which being electrically connected to the output circuit. The semiconductor device further includes an insulation film that is made of dielectric material and is provided between the at least one capacitor and the semiconductor substrate in a thickness direction of the semiconductor substrate.Type: ApplicationFiled: September 16, 2014Publication date: August 4, 2016Inventors: Takuya SUNADA, Yasushi KONISHI, Yu BUNGI, Yasuyoshi ASAI, Sachiko MUGIUDA
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Publication number: 20160035521Abstract: A circuit breaker 1 comprises: a fixed-contact piece 2 with a fixed contact 21; a movable-contact piece 4 with a movable contact 41; a thermal actuator element 5 thermally transformable to move the movable-contact piece so that the movable contact 41 and the fixed contact 21 are opened; a PTC thermistor 6 for conducting electricity between the movable-contact piece 4 and the fixed-contact piece 2 through the thermal actuator element 5 when the movable contact 41 and the fixed contact 21 are opened; a main body 71 of a package provided with a holding recess 73 housing the above-mentioned components; and a cover 81 hermetically covering the holding recess 73. The fixed-contact piece 2 is embedded between an internal wall 74 and an external wall 75 of the main body 71. The PTC thermistor 6 is housed in an opened hollow 73d penetrating through the internal wall 74 under such a state that the PTC thermistor 6 conductively contacts with the fixed-contact piece 2.Type: ApplicationFiled: July 29, 2015Publication date: February 4, 2016Applicant: KOMATSULITE MFG. CO., LTD.Inventors: Masashi NAMIKAWA, Takuya SUNADA
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Patent number: 9222808Abstract: In a radial optical path type rotary encoder, in order to be able to reduce deterioration of resolution and variation among products due to burrs during molding and/or rounding of a die, a scale for a rotary encoder is provided with a scale body which is formed substantially in a cylindrical shape, the scale body having a side surface portion in which a light transmitting portion through which light passes and a light blocking portion by which light with a predetermined width in a circumferential direction is blocked are formed alternately in the circumferential direction, wherein the side surface on a light-incident side of the light blocking portion is formed outside a light transmittable region having an outer edge defined by a light beam tangent to the side surface of the light blocking portion amidst the light passing through the light transmitting portion, in a lateral cross-section view.Type: GrantFiled: June 7, 2012Date of Patent: December 29, 2015Assignees: Kodenshi Corporation, Komatsulite Mfg. Co., Ltd.Inventors: Hideji Fukuda, Takuya Sunada
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Patent number: 8933394Abstract: A semiconductor device includes one or more transistor cells mounted on a first conductive type silicon carbide (SiC) substrate, wherein each of the transistor cells includes a second conductive type wall region formed on a first surface of the SiC substrate, a first conductive type source region formed in the wall region, a gate electrode formed with a gate insulating film; a source electrode formed in such a way as to be brought into contact with the source region, and a drain electrode formed on a second surface of the SiC substrate. The semiconductor device further includes a second conductive type region located close to an outside of an outermost cell of the transistor cells, the second conductive type region surrounding the wall region and being insulated from both of the gate electrode and the source electrode.Type: GrantFiled: February 23, 2011Date of Patent: January 13, 2015Assignee: Panasonic CorporationInventors: Hiroshi Okada, Takuya Sunada, Takeshi Oomori
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Patent number: 8803161Abstract: A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.Type: GrantFiled: February 23, 2011Date of Patent: August 12, 2014Assignee: Panasonic CorporationInventors: Hiroshi Okada, Takuya Sunada, Takeshi Oomori
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Publication number: 20140091212Abstract: In a radial optical path type rotary encoder, in order to be able to reduce deterioration of resolution and variation among products due to burrs during molding and/or rounding of a die, a scale for a rotary encoder is provided with a scale body which is formed substantially in a cylindrical shape, the scale body having a side surface portion in which a light transmitting portion through which light passes and a light blocking portion by which light with a predetermined width in a circumferential direction is blocked are formed alternately in the circumferential direction, wherein the side surface on a light-incident side of the light blocking portion is formed outside a light transmittable region having an outer edge defined by a light beam tangent to the side surface of the light blocking portion amidst the light passing through the light transmitting portion, in a lateral cross-section view.Type: ApplicationFiled: June 7, 2012Publication date: April 3, 2014Applicants: KOMATSULITE MFG. CO., LTD., KODENSHI CORPORATIONInventors: Hideji Fukuda, Takuya Sunada
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Publication number: 20130069082Abstract: A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.Type: ApplicationFiled: February 23, 2011Publication date: March 21, 2013Applicant: PANASONIC CORPORATIONInventors: Hiroshi Okada, Takuya Sunada, Takeshi Oomori
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Publication number: 20130033300Abstract: A semiconductor device includes one or more transistor cells mounted on a first conductive type silicon carbide (SiC) substrate, wherein each of the transistor cells includes a second conductive type wall region formed on a first surface of the SiC substrate, a first conductive type source region formed in the wall region, a gate electrode formed with a gate insulating film; a source electrode formed in such a way as to be brought into contact with the source region, and a drain electrode formed on a second surface of the SiC substrate. The semiconductor device further includes a second conductive type region located close to an outside of an outermost cell of the transistor cells, the second conductive type region surrounding the wall region and being insulated from both of the gate electrode and the source electrode.Type: ApplicationFiled: February 23, 2011Publication date: February 7, 2013Applicant: PANASONIC CORPORATIONInventors: Hiroshi Okada, Takuya Sunada, Takeshi Oomori
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Patent number: 7968943Abstract: Plural through-holes are formed in a region of a semiconductor substrate positioned below a drain region (an element region other than a P-type well region). According to this configuration, an opposing area of the drain region and the semiconductor substrate can be reduced. Therefore, a drain-substrate capacitance Cdsub is reduced, and an output capacitance Coss of an SOI LDMOSFET can be reduced as a result.Type: GrantFiled: May 29, 2009Date of Patent: June 28, 2011Assignee: Panasonic Electric Works Co., Ltd.Inventors: Takuya Sunada, Kazuhiko Kusuda, Takeshi Yoshida
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Publication number: 20090321827Abstract: Plural through-holes are formed in a region of a semiconductor substrate positioned below a drain region (an element region other than a P-type well region). According to this configuration, an opposing area of the drain region and the semiconductor substrate can be reduced. Therefore, a drain-substrate capacitance Cdsub is reduced, and an output capacitance Coss of an SOI LDMOSFET can be reduced as a result.Type: ApplicationFiled: May 29, 2009Publication date: December 31, 2009Applicant: PANASONIC ELECTRIC WORKS CO., LTD.Inventors: Takuya SUNADA, Kazuhiko KUSUDA, Takeshi YOSHIDA
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Patent number: 6930870Abstract: The semiconductor device is inserted between a power source and a load. A current flowing between an external drain terminal D and an external source terminal S is controlled in accordance with a control voltage applied between an external gate terminal G and the external source terminal S. In addition, the semiconductor device has a main MOSFET 1 and a detecting MOSFET 2 each of which is inserted between the external drain terminal D and the external source terminal S, a protective circuit 3 which protects the main MOSFET 1 by a protective transistor 5 when the abnormality is detected thereby, and an impedance element 4 inserted between the protective MOSFET 5, and a junction connecting the external gate terminal G to a gate electrode of the detecting MOSFET 2.Type: GrantFiled: September 27, 2001Date of Patent: August 16, 2005Assignee: Matsushita Electric Works, Ltd.Inventors: Takeshi Nobe, Shigeo Akiyama, Noriteru Furumoto, Takuya Sunada
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Publication number: 20040051145Abstract: The semiconductor device is inserted between a power source and a load. A current flowing between an external drain terminal D and an external source terminal S is controlled in accordance with a control voltage applied between an external gate terminal G and the external source terminal S. In addition, the semiconductor device has a main MOSFET 1 and a detecting MOSFET 2 each of which is inserted between the external drain terminal D and the external source terminal S, a protective circuit 3 which protects the main MOSFET 1 by a protective transistor 5 when the abnormality is detected thereby, and an impedance element 4 inserted between the protective MOSFET 5, and a junction connecting the external gate terminal G to a gate electrode of the detecting MOSFET 2.Type: ApplicationFiled: March 18, 2003Publication date: March 18, 2004Inventors: Takeshi Nobe, Shigeo Akiyama, Noriteru Furumoto, Takuya Sunada
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Patent number: 4655114Abstract: A plurality of envelope generating circuits provide output envelope waveforms which are controlled according to the output from a plurality of timbre switches. The envelope waveform of at least one of the envelope generating circuits is modified according to a touch data output of a touch data detecting circuit for detecting a way of operation of a performance key.Type: GrantFiled: July 23, 1984Date of Patent: April 7, 1987Assignee: Casio Computer Co., Ltd.Inventor: Takuya Sunada
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Patent number: 4612839Abstract: In response to the data input from a keyboard, a tone clock generator generates a tone clock signal. The tone clock signal is counted by a waveform step counter. The output of the counter is used for making an access to a waveform memory. The waveform memory stores first and second waveform data of which the periods respectively are divided into a different number of addresses. One of the first and second waveform data read out from the waveform memory by the output of the counter is selected, according to the key-in data.Type: GrantFiled: January 17, 1986Date of Patent: September 23, 1986Assignee: Casio Computer Co., Ltd.Inventor: Takuya Sunada
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Patent number: 4563932Abstract: A note ROM is addressed in response to a note code signal generated from a note code generator, and basic data is read out from the note ROM. The basic data is shifted by one higher bit and is thus doubled, and the shifted data is supplied to the A terminals of a full-adder. The basic data read out from the note ROM is supplied to the B terminals of the full-adder. The full-adder generates integer multiple data which has a value three times that of the basic data. This integer multiple data is decremented by one every time a clock is generated. When the integer multiple data becomes zero, a one-shot waveform data read clock signal is generated through an inverter.Type: GrantFiled: March 26, 1984Date of Patent: January 14, 1986Assignee: Casio Computer Co., Ltd.Inventor: Takuya Sunada
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Patent number: 4506581Abstract: The present invention provides a touch response apparatus for an electronic keyboard instrument wherein, in controlling a touch response state by detecting a key depression speed in the electronic keyboard instrument, the touch response states of keys are detected by detection means smaller in number than the keys, and the difference of detection outputs attributed to the different mounting positions of the contacts of a white key and a black key is also compensated.Type: GrantFiled: June 14, 1983Date of Patent: March 26, 1985Assignee: Casio Computer Co., Ltd.Inventor: Takuya Sunada