Abstract: [Objective] To provide a multilayer wiring substrate in which, even when a core substrate is thinned, the core substrate can reliably accommodate a capacitor. [Means for Solution] A multilayer wiring substrate 10 includes a sheetlike capacitor element 101, a resin filler 92, and via conductors 43 and 47. A sheetlike capacitor element 101 has an element main-surface 102 and an element back-surface 103, is configured such that a dielectric layer 107 is sandwiched directly between a main-surface-side electrode layer 105 exposed at the element main-surface 102 side and a back-surface-side electrode layer 106 exposed at the element back-surface 103 side, and is accommodated at least partially in an accommodation hole 90 such that a core main-surface 12 and the element main-surface 102 face the same direction. A resin filler 92 is charged into a gap between the sheetlike capacitor element 101 and an inner wall surface 91 of the accommodation hole 90.

Abstract: A wiring substrate is configured such that each of laminate portions provided above and below a substrate core includes insulating layers and conductor layers stacked alternately. Of the conductor layers of the laminate portions, signal line layers are treated with a silane coupling treatment, which is a surface modification treatment, so that each signal line comprises a flat surface. A roughening treatment is performed on the remaining conductor layers of the laminate portions such that the surfaces of these layers are roughened. This structure provides an advantage when high-frequency signals are transmitted through the signal line layers. That is, when each signal line comprises a flat surface, an increase in conductor loss due to the skin effect can be prevented. In addition, by means of chemical bonding attained through the silane coupling treatment, the reliability of adhesion between the signal line layers and the insulating layer is sufficiently attained.

Abstract: A multilayer wiring substrate includes first principal surface side connection terminals arranged on a first principal surface of a stacked configuration; wherein, the first principal surface side connection terminals include an IC chip connection terminal, and a passive element connection terminal; the IC chip connection terminal is located in an opening formed in a resin insulating layer of an uppermost outer layer; the passive element connection terminal is formed of an upper terminal part formed on the resin insulating layer, and a lower terminal part located in an opening formed at a portion of an inner side of the upper terminal part in the resin insulating layer; and, wherein an upper face of the upper terminal part is higher than a reference surface, and an upper face of the IC chip connection terminal and the lower terminal part are identical in height to or lower in height than the reference surface.

Abstract: A method of fabricating a wiring board including at least one conductor layer and at least one resin insulating layer, the method including a wiring groove forming step of forming a wiring groove in the resin insulating layer by irradiating a surface of the resin insulating layer with a laser, and a wiring layer forming step of forming the conductor layer such that at least a portion of the conductor layer is embedded in the wiring groove to form a wiring layer in the wiring groove.

Abstract: A method for manufacturing a wiring substrate having excellent connection reliability which has a front surface and a back surface and allows a semiconductor chip to be mounted on the front surface is provided. The method includes a step of forming build-up layers on a front side toward the front surface and a back side toward the back surface, respectively, by laminating one or more conductive layers and one or more resin insulation layers, the build-up layers on the front and back sides having at least one connection terminal on their surfaces, and a step of forming a first solder resist layer by laminating a first solder resist film on the build-up layer on the front side, and forming a second solder resist layer by laminating a second solder resist film thicker than the first solder resist layer on the build-up layer on the back side.

Abstract: A wiring substrate is configured such that each of laminate portions provided above and below a substrate core includes insulating layers and conductor layers stacked alternately. Of the conductor layers of the laminate portions, signal line layers are treated with a silane coupling treatment, which is a surface modification treatment, so that each signal line comprises a flat surface. A roughening treatment is performed on the remaining conductor layers of the laminate portions such that the surfaces of these layers are roughened. This structure provides an advantage when high-frequency signals are transmitted through the signal line layers. That is, when each signal line comprises a flat surface, an increase in conductor loss due to the skin effect can be prevented. In addition, by means of chemical bonding attained through the silane coupling treatment, the reliability of adhesion between the signal line layers and the insulating layer is sufficiently attained.

Abstract: A method of fabricating a wiring board including at least one conductor layer and at least one resin insulating layer, the method including a wiring groove forming step of forming a wiring groove in the resin insulating layer by irradiating a surface of the resin insulating layer with a laser, and a wiring layer forming step of forming the conductor layer such that at least a portion of the conductor layer is embedded in the wiring groove to form a wiring layer in the wiring groove.

Abstract: A multilayer wiring substrate includes first principal surface side connection terminals arranged on a first principal surface of a stacked configuration; wherein, the first principal surface side connection terminals include an IC chip connection terminal, and a passive element connection terminal; the IC chip connection terminal is located in an opening formed in a resin insulating layer of an uppermost outer layer; the passive element connection terminal is formed of an upper terminal part formed on the resin insulating layer, and a lower terminal part located in an opening formed at a portion of an inner side of the upper terminal part in the resin insulating layer; and, wherein an upper face of the upper terminal part is higher than a reference surface, and an upper face of the IC chip connection terminal and the lower terminal part are identical in height to or lower in height than the reference surface.