Abstract: A flight management system for a plurality of aerial vehicles includes a management apparatus and an operation terminal. The management apparatus includes processing circuitry to manage operation authorizations to operate the plurality of aerial vehicles. The operation terminal includes an operation interface and processing circuitry. The operation interface is operable by an operator. The processing circuit is connected to the operation interface. Based on an authorization grant request signal obtained based on a flight state of each aerial vehicle of the plurality of aerial vehicles, the processing circuit of the management apparatus transmits an authorization grant command to grant the operation terminal an operation authorization, among the operation authorizations, that is to operate a particular aerial vehicle among the plurality of aerial vehicles.

Abstract: A circuit simulation apparatus and a modeling method are provided which are useful to design an integrated circuit in a very fine manner by forming a model of such a transistor that widths of element isolating-purpose insulating films are different from each other. In an isolation width depending parameter correcting means 4 of the present invention, an approximate expression of a parameter having an element isolating-purpose insulating film width depending characteristic is formed, and a value of a corrected parameter obtained by employing the formed approximate expression is replaced by a value of an original parameter, so that a transistor model of such a transistor is formed in which element isolating-purpose insulating film widths are different from each other. As a consequence, circuit simulation can be carried out in high precision by considering a change in transistor characteristics caused by a stress, which are approximated to actually measured data.

Abstract: A circuit extracting apparatus or method of the present invention extracts circuit information which allows a drain current and a gate capacitance in an actual device to be reproduced with high fidelity in circuit simulation. Transistor-portion-configuration recognizing means recognizes the configuration of a transistor portion in the mask layout of a semiconductor circuit so as to generate transistor-portion-configuration data. Transistor-size calculating means calculates an equivalent transistor size based on the transistor-portion-configuration data, such that a drain current in the circuit simulation coincides with the drain current in the actual device. Corrective-capacitance generating means obtains the difference between a gate capacitance in the circuit simulation using the equivalent transistor size and the gate capacitance in the actual device so as to virtually generate a corrective capacitance having a capacitance value corresponding to the obtained difference.