Abstract: A travel control device assists automatic traveling of a vehicle by controlling a target vehicle speed, which is a target value of an actual vehicle speed, when making the vehicle travel to a target point. The travel control device includes a setting unit for executing a setting process for setting the course of the target vehicle speed until the vehicle reaches the target point, based on the actual vehicle speed and the target point. If a request to change the vehicle speed occurs during execution of the automatic traveling and the actual vehicle speed is changed based on the request, the setting unit executes a resetting process for resetting the course of the target vehicle speed, based on the actual vehicle speed when the request is canceled and a remaining distance from a position of the vehicle when the request is canceled to the target point.

Abstract: A control device is provided with: a moving distance estimation unit that calculates an estimated value of a vehicle moving distance on the basis of a pulse signal inputted from a wheel speed sensor and a wheel dynamic load radius stored in a storage unit; a moving distance deriving unit that derives the calculated value of the vehicle moving distance on the basis of information acquired by monitoring systems; a vehicle stop position setting unit that sets a target vehicle stop position on the basis of the information acquired by the monitoring systems; a correction unit that corrects the target vehicle stop position on the basis of the calculated value of the moving distance and the estimated value of the moving distance; and a brake control unit that assists vehicle stoppage so as to stop the vehicle when it is determined that the vehicle has reached the target vehicle stop position on the basis of the vehicle moving distance calculated from a wheel rotation amount and the target vehicle stop position.

Abstract: A control device for a vehicle includes: an accepting unit configured to accept a first braking request from a plurality of applications that realize a driving assistance function; an acquiring unit configured to acquire a second braking request by a driver operation; an arbitrating unit configured to perform arbitration of the first braking request and the second braking request; and an output unit configured to output a request to an actuator based on a result of the arbitration by the arbitrating unit, wherein the arbitrating unit is configured to, when the acquiring unit acquires the second braking request while the output unit is outputting the request to the actuator, perform the arbitration in which the request that the output unit outputs to the actuator is increased or maintained, based on the second braking request.

Abstract: A travel control device assists automatic traveling of a vehicle by controlling a target vehicle speed, which is a target value of an actual vehicle speed, when making the vehicle travel to a target point. The travel control device includes a setting unit for executing a setting process for setting the course of the target vehicle speed until the vehicle reaches the target point, based on the actual vehicle speed and the target point. If a request to change the vehicle speed occurs during execution of the automatic traveling and the actual vehicle speed is changed based on the request, the setting unit executes a resetting process for resetting the course of the target vehicle speed, based on the actual vehicle speed when the request is canceled and a remaining distance from a position of the vehicle when the request is canceled to the target point.

Abstract: A control device is provided with: a moving distance estimation unit that calculates an estimated value of a vehicle moving distance on the basis of a pulse signal inputted from a wheel speed sensor and a wheel dynamic load radius stored in a storage unit; a moving distance deriving unit that derives the calculated value of the vehicle moving distance on the basis of information acquired by monitoring systems; a vehicle stop position setting unit that sets a target vehicle stop position on the basis of the information acquired by the monitoring systems; a correction unit that corrects the target vehicle stop position on the basis of the calculated value of the moving distance and the estimated value of the moving distance; and a brake control unit that assists vehicle stoppage so as to stop the vehicle when it is determined that the vehicle has reached the target vehicle stop position on the basis of the vehicle moving distance calculated from a wheel rotation amount and the target vehicle stop position.

Abstract: The present invention provides an antifouling coating material which can be used to form an antifouling coating film excellent in long-term antifouling performance and physical properties, and which is excellent in long-term storage stability. The present invention provides an antifouling coating composition containing a copolymer [A] obtained by copolymerizing a monomer represented by a general formula (1) (wherein, X represents acryloyloxy, methacryloyloxy, crotonoyloxy, or isocrotonoyloxy, R1 represents a hydrogen atom or methyl, and R2 represents an alkyl group having a carbon number of 1 to 6), and a polymerizable monomer represented by a general formula (2) (wherein, R3 represents a hydrogen atom or methyl, R4 represents an alkyl group having a carbon number of 1 to 10, or an alkyl group having a carbon number of 2 to 5 to which an alkoxy group having a carbon number of 1 to 4 is bonded.).

Abstract: A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.

Abstract: Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.

Abstract: An insulating circuit board includes an insulating plate, a circuit board joined to a first surface of the insulating plate, and a metal plate joined to a second surface of the insulating plate. The circuit board is formed from an Al alloy having a purity of 99.98% or more or pure Al, and the metal plate is formed from an Al alloy having a purity of 98.00% or more and 99.90% or less. The thickness (a) of the circuit board is 0.2 mm or more and 0.8 mm or less, the thickness (b) of the metal plate is 0.6 mm or more and 1.5 mm or less, and the thicknesses satisfy the expression of a/b?1. An insulating circuit board having a cooling sink includes cooling sink joined via a second solder layer. The second solder layer contains Sn as its main component, and has a Young's modulus, 35 GPa or more, a 0.2% proof stress of, 30 MPa or more, and a tensile strength of, 40 MPa or more. The cooling sink is formed from, pure Al or an Al alloy.

Abstract: A method is provided for designing a wiring structure of a wiring layer of a semiconductor integrated circuit device. The method includes a wire width detecting step of detecting a wire width of each wire in a wiring pattern of layout data, a wire identifying step of identifying a wire having a predetermined wire width or more based on a result of detection by the wire width detecting step, a wiring pitch detecting step of detecting a wiring pitch between the wire identified by the wire identifying step and another wire, and an air gap-forbidden region forming and removing step of forming or removing an air gap-forbidden region, depending on a result of detection by the wiring pitch detecting step.

Abstract: Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.

Abstract: In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.

Abstract: An automatic layout method of a semiconductor integrated circuit includes an initial arranging step for initially arranging a logic cell which constitutes the logic circuit; a placement base circuit optimizing step for applying a margin of a constant length to a wiring line length obtained from a placement so as to improve timing; an placement change restriction calculating step for calculating a placement change restriction corresponding to the margin of the constant length; and an incremental arranging step in which when a logic cell placement of a corrected logic circuit is improved, a placement improvement having the placement change restriction calculated based upon the placement change restriction calculating step is carried out.

Abstract: In a layout designing operation of LSI, while repetitions as to a timing improvement and a retry of layout designing are suppressed, a designing term is shortened. An automatic layout method of a semiconductor integrated circuit is comprised of: an initial arranging step for initially arranging a logic cell which constitutes the logic circuit; an placement base circuit optimizing step for applying a margin of a constant length to a wiring line length obtained from an placement so as to improve timing; an placement change restriction calculating step for calculating an placement change restriction corresponding to the margin of the constant length; and an incremental arranging step in which when a logic cell placement of a corrected logic circuit is improved, an placement improvement having the placement change restriction calculated based upon the placement change restriction calculating step is carried out.

Abstract: Formerly, in a microfabrication process of a semiconductor integrated circuit, there has been a problem of occurrence of a malfunction of a circuit during a scan test due to a skew resulting from factors, such as manufacturing variation and a delay calculation error, which have not been detected in simulation. In the present invention, for a plurality of flip-flop circuits which configure a scan chain, by arranging a clock circuit for scan which supplies a clock signal during the scan test separately from a clock circuit for normal operation which supplies a clock signal during a normal operation, arranging a lattice-shaped wiring portion for the clock circuit for scan, and supplying the clock signal for scan to each flip-flop circuit from the lattice-shaped wiring portion, generation of the clock skew resulting from the effect of the delay calculation error or the manufacturing variation in the microfabrication process is prevented, thereby preventing the malfunction during the scan test.

Abstract: In design of particularly large-scale, complicated semiconductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.

Abstract: In design of particularly large-scale, complicated semiconductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.

Abstract: In design of particularly large-scale, complicated semi-conductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.

Abstract: Based on the arrangement of a plurality of synchronous devices in an integrated circuit or on timing constraints, a group of discrete clock delay values composed of a finite number of discrete values to be allocated as respective clock delay values to the individual synchronous devices is determined. Then, the clock delay value selected from the group of discrete clock delay values is allocated as a selected clock delay value to each of the synchronous devices, while the operation of the integrated circuit is ensured. Thereafter, a clock circuit for supplying a clock signal to each of the synchronous devices in accordance with the selected clock delay value is designed.

Abstract: In design of particularly large-scale, complicated semiconductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.