Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.

Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.

Abstract: The object is to provide a technique for enabling determination of an appropriate test condition. A test condition determining apparatus includes a map generating unit, a withstand voltage estimating unit, and a test condition determining unit. The map generating unit generates a wafer map relevant to a plurality of chips, based on measurement values of thicknesses and carrier concentrations of an epitaxial growth layer, and measurement results of crystal defects in the epitaxial growth layer and a substrate. The withstand voltage estimating unit estimates a withstand voltage of each of the chips based on the wafer map. The test condition determining unit determines a test condition of a test to be conducted on the chips, based on a result of the estimation made by the withstand voltage estimating unit.

Abstract: A silicon carbide epitaxial wafer includes a silicon carbide substrate and silicon carbide epitaxial layers formed on the silicon carbide substrate. Each of the silicon carbide epitaxial layers has a triangular defect. The silicon carbide epitaxial layer each have a step inside the triangular defect in the surface morphology of the triangular defect.

Abstract: The object is to provide a technique for enabling determination of an appropriate test condition. A test condition determining apparatus includes a map generating unit, a withstand voltage estimating unit, and a test condition determining unit. The map generating unit generates a wafer map relevant to a plurality of chips, based on measurement values of thicknesses and carrier concentrations of an epitaxial growth layer, and measurement results of crystal defects in the epitaxial growth layer and a substrate. The withstand voltage estimating unit estimates a withstand voltage of each of the chips based on the wafer map. The test condition determining unit determines a test condition of a test to be conducted on the chips, based on a result of the estimation made by the withstand voltage estimating unit.

Abstract: The present invention is aimed at providing a method of manufacturing a silicon carbide epitaxial wafer by which a plurality of silicon carbide epitaxial layers of a predetermined layer thickness can be precisely formed. In the present invention, a first n-type SiC epitaxial layer is formed on an n-type SiC substrate so that the rate of change in impurity concentration between the n-type SiC substrate and the first n-type SiC epitaxial layer will be greater than or equal to 20%. A second n-type SiC epitaxial layer is formed on the first n-type SiC epitaxial layer so that the rate of change in impurity concentration between the first n-type SiC epitaxial layer and the second n-type SiC epitaxial layer will be greater than or equal to 20%.

Abstract: The present invention is aimed at providing a method of manufacturing a silicon carbide epitaxial wafer by which a plurality of silicon carbide epitaxial layers of a predetermined layer thickness can be precisely formed. In the present invention, a first n-type SiC epitaxial layer is formed on an n-type SiC substrate so that the rate of change in impurity concentration between the n-type SiC substrate and the first n-type SiC epitaxial layer will be greater than or equal to 20%. A second n-type SiC epitaxial layer is formed on the first n-type SiC epitaxial layer so that the rate of change in impurity concentration between the first n-type SiC epitaxial layer and the second n-type SiC epitaxial layer will be greater than or equal to 20%.

Abstract: Provided is a method for manufacturing a silicon carbide semiconductor device capable of preventing an increase in a cost of manufacturing one chip while favorably maintaining forward characteristics of the semiconductor device including (a) inspecting the characteristics of the forward conduction of body diodes as element structures; (b) classifying the body diode and the body diode as either a first group suitable for forward conduction or a second group unsuitable for forward conduction on the basis of an inspection result; and (c) manufacturing a silicon carbide semiconductor MOSFET that requires forward conduction using the body diode classified into the first group or manufacturing a silicon carbide semiconductor MOSFET that does not need forward conduction using the body diode classified into the second group.

Abstract: It is an object of the present invention to provide a method for manufacturing a silicon carbide semiconductor device capable of preventing an increase in a cost of manufacturing one chip while favorably maintaining forward characteristics of the semiconductor device. The present invention includes the steps of: (a) inspecting the characteristics of the forward conduction of body diodes as element structures; (b) classifying the body diode and the body diode as a first group suitable for the forward conduction or a second group unsuitable for the forward conduction on the basis of an inspection result of the step (a); and (c) manufacturing a silicon carbide semiconductor MOSFET that needs the forward conduction using the body diode of the first group or manufacturing a silicon carbide semiconductor MOSFET that does not need the forward conduction using the body diode of the second group.

Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.

Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.

Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.

Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.