Patents by Inventor Tal Abir
Tal Abir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260186858Abstract: The disclosure includes a virtual sparse bit-array (VSB) having a low memory structure. The low memory structure is designed to increase processing speed for operations executed on the VSB. The VSB may be in a pointer tree structure or an offset tree structure. The VSB includes blocks, levels, and special pointers. The blocks are distributed on the levels to form the tree structure. The special pointers include a real pointer that connects the blocks across levels of the VSB tree structure, zero pointers which indicate all bits in the block and blocks connected to the block from levels below are reset to zero, and max pointers (FF), which indicate all bits in the block and blocks connected to the block from levels below are set to one. Methods herein describe how to allocate and deallocate sets of blocks at each level to achieve maximum memory efficiency.Type: ApplicationFiled: December 26, 2024Publication date: July 2, 2026Inventors: Dvir Koren, Tal Abir
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Publication number: 20260169804Abstract: Techniques are provided for responding to user requests to processor-based resources upon storage of request data to persistent data storage. One method comprises obtaining a request directed to a resource, wherein the a request identifies at least a portion of the resource; locking the at least the portion of the resource, wherein the locking prevents one or more additional requests from being processed for the at least the portion of the resource; updating a data portion associated with the request in a persistent storage device; sending, in response to the updating the data portion associated with the request in the persistent storage device, a response to the request; performing at least one designated post-response task for the request; and releasing the locked at least the portion of the resource, in response to a completion of the at least one designated post-response task.Type: ApplicationFiled: December 16, 2024Publication date: June 18, 2026Inventors: Dvir Koren, Tal Abir, Avi Puder
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Publication number: 20260086867Abstract: Techniques are provided for penalty-based management of requests for processor-based resources. One method comprises obtaining a request, from a given user, directed to a given processor-based resource; determining a penalty associated with the request, wherein the penalty is based on a resource utilization associated with one or more requests directed to the given processor-based resource and wherein the penalty indicates an amount of time that the given user waits before sending at least one additional request to the given processor-based resource; generating a response to the request, wherein the response comprises the determined penalty; and providing the generated response to the given user. The penalty may be determined based on an amount of bandwidth utilized in a designated time interval relative to a configured bandwidth limit for the designated time interval.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Inventors: Dvir Koren, Guy Fayzak, Tal Abir
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Patent number: 12572409Abstract: Techniques are provided for identifying anomalous portions of input/output (I/O) paths by monitoring checkpoints of I/O operations through a storage system. One method comprises obtaining checkpoint data associated with designated storage volumes in a storage system that comprises designated storage system components. The checkpoint data may be associated with multiple I/O operations that are processed by the designated storage system components and the checkpoint data for a given I/O operation may comprise checkpoint times indicating respective times that the given I/O operation is processed by a corresponding designated storage system component. A time difference between two checkpoint times may be evaluated to identify anomalous portions of an I/O path between the designated storage system components associated with the two checkpoint times. One or more automated actions may be performed related to the designated storage system components associated with the anomalous portions of the I/O path.Type: GrantFiled: May 20, 2024Date of Patent: March 10, 2026Assignee: Dell Products L.P.Inventors: Dvir Koren, Tal Abir
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Publication number: 20250355749Abstract: Techniques are provided for identifying anomalous portions of input/output (I/O) paths by monitoring checkpoints of I/O operations through a storage system. One method comprises obtaining checkpoint data associated with designated storage volumes in a storage system that comprises designated storage system components. The checkpoint data may be associated with multiple I/O operations that are processed by the designated storage system components and the checkpoint data for a given I/O operation may comprise checkpoint times indicating respective times that the given I/O operation is processed by a corresponding designated storage system component. A time difference between two checkpoint times may be evaluated to identify anomalous portions of an I/O path between the designated storage system components associated with the two checkpoint times. One or more automated actions may be performed related to the designated storage system components associated with the anomalous portions of the I/O path.Type: ApplicationFiled: May 20, 2024Publication date: November 20, 2025Inventors: Dvir Koren, Tal Abir
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Publication number: 20250291779Abstract: Techniques are provided for metadata page allocation by storing a portion of a bitmap of metadata pages in memory. One method comprises obtaining a request to allocate metadata pages of a metadata storage volume; identifying at least one bit, corresponding to an unallocated metadata page, in a given chunk of a bitmap of metadata pages associated with the metadata storage volume, wherein the given chunk of the bitmap is stored in memory and comprises a portion of the bitmap; updating a bit value of the identified at least one bit to indicate the allocation of the metadata pages of the metadata storage volume; and initiating an allocation of the metadata pages. The bitmap may be allocated to a designated size, and each bit of the bitmap may indicate whether a corresponding metadata page of the metadata storage volume is allocated or unallocated.Type: ApplicationFiled: March 14, 2024Publication date: September 18, 2025Inventors: Oran Baruch, Tal Abir
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Patent number: 12032830Abstract: An apparatus includes at least one processing device configured to identify a logical storage volume stored across multiple storage nodes of a distributed storage system, to obtain address range distribution information for the logical storage volume from at least a subset of the storage nodes, the address range distribution information indicating, for each of a plurality of distinct address ranges of the logical storage volume, which of the storage nodes locally stores data for that address range, and to generate, from the obtained address range distribution information, a mapping of the distinct address ranges to particular ones of the storage nodes, wherein the mapping is utilized to select paths for delivery of input-output operations to the storage nodes. Obtaining address range distribution information for the logical storage volume may comprise, for example, sending log page commands to each of the storage nodes to obtain asymmetric range access and/or template information.Type: GrantFiled: April 27, 2022Date of Patent: July 9, 2024Assignee: Dell Products L.P.Inventors: Ziv Dor, Itay Keller, Rivka Mayraz Matosevich, Tal Abir
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Patent number: 11907537Abstract: First and second target controllers implemented in a storage system are associated with respective first and second storage pools having respective first and second service level objectives. Input-output (IO) operations are received from one or more host devices and processed in the storage system, with different ones of the IO operations being directed from one or more initiators of the one or more host devices to different ones of the first and second target controllers. Separate feedback information is provided from the storage system to the one or more host devices for respective ones of the first and second target controllers, so as to permit different amounts of throttling of additional IO operations in the one or more host devices based at least in part on whether those additional IO operations are to be directed to the first target controller or the second target controller.Type: GrantFiled: April 6, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Igor Achkinazi, Tal Abir
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Patent number: 11816340Abstract: Techniques are provided for increasing resiliency of IO operations to network interruptions. One method comprises, in response to a failure of a given IO operation on a first path between at least one initiator of a host device and at least one storage target of a storage volume of a distributed storage system, resending the given IO operation on a second path between the at least one initiator and the at least one storage target; and, in response to a completion of the given IO operation on a given one of the first path and the second path, initiating a remapping of the storage volume. The remapping of the storage volume may comprise unmapping the storage volume and mapping the storage volume. One or more IO operations having an older generation number than the generation number of the storage volume may be discarded.Type: GrantFiled: February 28, 2022Date of Patent: November 14, 2023Assignee: Dell Products L.P.Inventors: Tal Abir, Oshri Adler
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Publication number: 20230350572Abstract: An apparatus includes at least one processing device configured to identify a logical storage volume stored across multiple storage nodes of a distributed storage system, to obtain address range distribution information for the logical storage volume from at least a subset of the storage nodes, the address range distribution information indicating, for each of a plurality of distinct address ranges of the logical storage volume, which of the storage nodes locally stores data for that address range, and to generate, from the obtained address range distribution information, a mapping of the distinct address ranges to particular ones of the storage nodes, wherein the mapping is utilized to select paths for delivery of input-output operations to the storage nodes. Obtaining address range distribution information for the logical storage volume may comprise, for example, sending log page commands to each of the storage nodes to obtain asymmetric range access and/or template information.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Inventors: Ziv Dor, Itay Keller, Rivka Mayraz Matosevich, Tal Abir
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Publication number: 20230325084Abstract: First and second target controllers implemented in a storage system are associated with respective first and second storage pools having respective first and second service level objectives. Input-output (IO) operations are received from one or more host devices and processed in the storage system, with different ones of the IO operations being directed from one or more initiators of the one or more host devices to different ones of the first and second target controllers. Separate feedback information is provided from the storage system to the one or more host devices for respective ones of the first and second target controllers, so as to permit different amounts of throttling of additional IO operations in the one or more host devices based at least in part on whether those additional IO operations are to be directed to the first target controller or the second target controller.Type: ApplicationFiled: April 6, 2022Publication date: October 12, 2023Inventors: Igor Achkinazi, Tal Abir
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Publication number: 20230273730Abstract: Techniques are provided for increasing resiliency of IO operations to network interruptions. One method comprises, in response to a failure of a given IO operation on a first path between at least one initiator of a host device and at least one storage target of a storage volume of a distributed storage system, resending the given IO operation on a second path between the at least one initiator and the at least one storage target; and, in response to a completion of the given IO operation on a given one of the first path and the second path, initiating a remapping of the storage volume. The remapping of the storage volume may comprise unmapping the storage volume and mapping the storage volume. One or more IO operations having an older generation number than the generation number of the storage volume may be discarded.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: Tal Abir, Oshri Adler
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Patent number: 11693600Abstract: Techniques are provided for latency-based detection of storage volume type. One method comprises sending read commands using a predefined read command sequence to a recipient storage volume, wherein the predefined read command sequence specifies a request size and/or an offset of at least two of the read commands, and wherein an entity associated with a recipient storage volume of a predefined storage volume type is configured to insert a predefined delay before sending a response to at least one of the read commands when the entity detects the predefined read command sequence; evaluating whether the response to at least one of the read commands comprises the predefined delay; and determining whether the recipient storage volume is the predefined storage volume type based on a result of the evaluating. The recipient storage volume may comprise a storage volume and/or a storage data client that exposes a virtual storage volume.Type: GrantFiled: February 28, 2022Date of Patent: July 4, 2023Assignee: Dell Products L.P.Inventors: Oshri Adler, Tal Abir
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Patent number: 7430574Abstract: Methods are disclosed to implement bit scan operations using properties of two's complement arithmetic and compute zero index instructions. A data value may be provided and the most-significant or least-significant bit may be determined using the methods set forth herein.Type: GrantFiled: June 24, 2004Date of Patent: September 30, 2008Assignee: Intel CorporationInventors: Mauricio Breternitz, Jr., Youfeng Wu, Tal Abir
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Publication number: 20050289203Abstract: Methods are disclosed to implement bit scan operations using properties of two's complement arithmetic and compute zero index instructions. A data value may be provided and the most-significant or least-significant bit may be determined using the methods set forth herein.Type: ApplicationFiled: June 24, 2004Publication date: December 29, 2005Inventors: Mauricio Breternitz, Youfeng Wu, Tal Abir