Patents by Inventor Tal Erlich

Tal Erlich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STIMULATION OF HAIR GROWTH
    Publication number: 20230293451
    Abstract: Compositions and methods that can increase or stimulate hair growth, as well as novel chemicals that affect hair growth and hair loss.
    Type: Application
    Filed: January 8, 2021
    Publication date: September 21, 2023
    Inventors: David E. Fisher, Xu Wu, Mack Su, Tal Erlich
  • Optimization of verification of chip design
    Patent number: 8214780
    Abstract: Embodiments of methods and apparatus for optimization of verification of a chip design are disclosed. In various embodiments, a method for reducing a number of points to be verified during a verification process is disclosed, the method comprising selecting a first and a second verification point of a model of an integrated circuit design, determining whether the first and second verification points are isomorphic, and outputting the result of the determining to enable the first and second verification points being verified by verifying only a selected one of the first and second verification points in case the first and the second verification points are isomorphic. Additional variants and embodiments may also be disclosed and claimed.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: July 3, 2012
    Assignee: Intel Corporation
    Inventors: Tal Erlich, Daher Kaiss, Maayan Fishelson
  • OPTIMIZATION OF VERIFICATION OF CHIP DESIGN
    Publication number: 20100058259
    Abstract: Embodiments of methods and apparatus for optimization of verification of a chip design are disclosed. In various embodiments, a method for reducing a number of points to be verified during a verification process is disclosed, the method comprising selecting a first and a second verification point of a model of an integrated circuit design, determining whether the first and second verification points are isomorphic, and outputting the result of the determining to enable the first and second verification points being verified by verifying only a selected one of the first and second verification points in case the first and the second verification points are isomorphic. Additional variants and embodiments may also be disclosed and claimed.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 4, 2010
    Inventors: Tal Erlich, Daher Kaiss, Maayan Fishelson