Patents by Inventor Tal Horowitz

Tal Horowitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for performing multiplication of one or more matrices using multi-thread systolic arrays
    Patent number: 12260248
    Abstract: A multi-thread systolic array includes a plurality of processing elements, each including a processor. Each of the processing elements is configured to: receive a plurality of first inputs from a respective first input source; receive a plurality of second inputs from a respective second input source; the plurality of first inputs and the plurality of second inputs being arranged as a plurality of pairs corresponding to a plurality of threads; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads; and execute a computation operation for the certain thread.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 25, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Tal Horowitz, Uri Weiser, Zuguang Wu, Huibin Luo, Yoni Choukroun
  • MULTI-THREAD SYSTOLIC ARRAY
    Publication number: 20200192701
    Abstract: A multi-thread systolic array includes a plurality of processing elements, each including a processor. Each of the processing elements is configured to: receive a plurality of first inputs from a respective first input source; receive a plurality of second inputs from a respective second input source; the plurality of first inputs and the plurality of second inputs being arranged as a plurality of pairs corresponding to a plurality of threads; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads; and execute a computation operation for the certain thread.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Inventors: Tal HOROWITZ, Uri WEISER, Zuguang WU, Huibin LUO, Yoni CHOUKROUN
  • Multi-multidimensional computer architecture for big data applications
    Patent number: 10417005
    Abstract: A data processing apparatus is provided comprising a front-end interface electronically coupled to a main processor. The front-end interface is configured to receive data stored in a repository, in particular an external storage and/or a network, determine whether the data is a single-access data or a multiple-access data by analyzing an access parameter designating the data, route the multiple-access data for processing by the main processor, and route the single-access data for pre-processing by the front-end interface and routing results of the pre-processing to the main processor.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 17, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Uri Weiser, Tal Horowitz, Jintang Wang
  • MULTI-MULTIDIMENSIONAL COMPUTER ARCHITECTURE FOR BIG DATA APPLICATIONS
    Publication number: 20170371676
    Abstract: A data processing apparatus is provided comprising a front-end interface electronically coupled to a main processor. The front-end interface is configured to receive data stored in a repository, in particular an external storage and/or a network, determine whether the data is a single-access data or a multiple-access data by analyzing an access parameter designating the data, route the multiple-access data for processing by the main processor, and route the single-access data for pre-processing by the front-end interface and routing results of the pre-processing to the main processor.
    Type: Application
    Filed: September 11, 2017
    Publication date: December 28, 2017
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Uri WEISER, Tal HOROWITZ, Jintang WANG
  • Systems and Methods For Efficient Handling of Data Traffic and Processing Within a Processing Device
    Publication number: 20160164807
    Abstract: The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power.
    Type: Application
    Filed: February 16, 2016
    Publication date: June 9, 2016
    Applicant: Commex Technologies, Ltd.
    Inventors: Yehiel ENGEL, Avraham GANOR, Tal HOROWITZ, Michael Chaim SCHNARCH, Yaron SHACHAR, Uri Chanan WEISER
  • Systems and methods for efficient handling of data traffic and processing within a processing device
    Patent number: 9268729
    Abstract: The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: February 23, 2016
    Assignee: Commex Technologies, Ltd.
    Inventors: Yehiel Engel, Avraham Ganor, Tal Horowitz, Michael Chaim Schnarch, Yaron Shachar, Uri Chanan Weiser
  • Systems and Methods For Efficient Handling of Data Traffic and Processing Within a Processing Device
    Publication number: 20130016729
    Abstract: The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power.
    Type: Application
    Filed: May 18, 2012
    Publication date: January 17, 2013
    Applicant: Commex Technologies, Ltd.
    Inventors: Yehiel Engel, Avraham Ganor, Tal Horowitz, Michael Chaim Schnarch, Yaron Shachar, Uri Chanan Weiser
  • Systems and methods for efficient handling of data traffic and processing within a processing device
    Patent number: 8209457
    Abstract: The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: June 26, 2012
    Assignee: Commex Technologies, Ltd.
    Inventors: Yehiel Engel, Avraham Ganor, Tal Horowitz, Michael Chaim Schnarch, Yaron Shachar, Uri Chanan Weiser
  • Systems and Methods for Efficient Handling of Data Traffic and Processing Within a Processing Device
    Publication number: 20100332713
    Abstract: The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power.
    Type: Application
    Filed: September 3, 2010
    Publication date: December 30, 2010
    Applicant: Commex Technologies, Ltd.
    Inventors: Yehiel Engel, Avraham Ganor, Tal Horowitz, Michael Chaim Schnarch, Yaron Shachar, Uri Chanan Weiser
  • Systems and methods for efficient handling of data traffic and processing within a processing device
    Patent number: 7793032
    Abstract: The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: September 7, 2010
    Assignee: Commex Technologies, Ltd.
    Inventors: Yehiel Engel, Avraham Ganor, Tal Horowitz, Michael Chaim Schnarch, Yaron Shachar, Uri Chanan Weiser
  • Systems and Methods for Efficient Handling of Data Traffic and Processing Within a Processing Device
    Publication number: 20090019206
    Abstract: The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 15, 2009
    Inventors: Yehiel Engel, Avraham Ganor, Tal Horowitz, Michael Chaim Schnarch, Yaron Shahar, Uri Chanan Weiser