Patents by Inventor Tal Klein

Tal Klein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automatic functional test pattern generation based on DUT reference model and unique scripts
    Patent number: 12561218
    Abstract: An apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a high-level verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: February 24, 2026
    Assignee: Winbond Electronics Corporation
    Inventors: Tal Klein, Ronny Aboutboul, Yoram Avigdor, Erez Glasberg
  • Automatic Functional Test Pattern Generation based on DUT Reference Model and Unique Scripts
    Publication number: 20230315598
    Abstract: An apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a high-level verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program.
    Type: Application
    Filed: April 5, 2022
    Publication date: October 5, 2023
    Inventors: Tal Klein, Ronny Aboutboul, Yoram Avigdor, Erez Glasberg