Abstract: Systems and method are provided for analyzing target, process and metrology configuration sensitivities to a wide range of parameters, according to external requirements or inner development and verification needs. Systems comprise the following elements. An input module is arranged to receive parameters relating to targets, target metrology conditions and production processes, to generate target data. A metrology simulation unit is arranged to simulate metrology measurements of targets from the target data and to generate multiple metrics that quantify the simulated target measurements. A sensitivity analysis module is arranged to derive functional dependencies of the metrics on the parameters and to define required uncertainties of the parameters with respect to the derived functional dependencies. Finally, a target optimization module is arranged to rank targets and target metrology conditions with respect to the simulated target measurements.

Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes.

Abstract: A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.

Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes.

Abstract: A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.

Abstract: Systems and method are provided for analyzing target, process and metrology configuration sensitivities to a wide range of parameters, according to external requirements or inner development and verification needs. Systems comprise the following elements. An input module is arranged to receive parameters relating to targets, target metrology conditions and production processes, to generate target data. A metrology simulation unit is arranged to simulate metrology measurements of targets from the target data and to generate multiple metrics that quantify the simulated target measurements. A sensitivity analysis module is arranged to derive functional dependencies of the metrics on the parameters and to define required uncertainties of the parameters with respect to the derived functional dependencies. Finally, a target optimization module is arranged to rank targets and target metrology conditions with respect to the simulated target measurements.