Abstract: In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to determine a lowest latency LAG port for each LAG in any path of a plurality of paths connecting a first device with a second device, and discover a configuration of a network fabric connecting the first device to the second device after determining the lowest latency LAG port for each LAG therein. The network fabric includes a plurality of devices interconnected with LAGs. Moreover, the embodied program instructions are executable by the processor to perform clock synchronization for each path of the plurality of paths and determine a latency for each path of the plurality of paths based on the clock synchronization and the lowest latency LAG port for each LAG included in the plurality of paths.

Abstract: In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to determine a lowest latency LAG port for each LAG in any path of a plurality of paths connecting a first device with a second device, and discover a configuration of a network fabric connecting the first device to the second device after determining the lowest latency LAG port for each LAG therein. The network fabric includes a plurality of devices interconnected with LAGs. Moreover, the embodied program instructions are executable by the processor to perform clock synchronization for each path of the plurality of paths and determine a latency for each path of the plurality of paths based on the clock synchronization and the lowest latency LAG port for each LAG included in the plurality of paths.

Abstract: In one embodiment, a system for determining latency in paths includes logic integrated with and/or executable by a processor, the logic being adapted to synchronize clocks of two devices connected via two or more link aggregation (LAG) ports and/or multiple devices within paths through a network fabric, determine a transit delay for each LAG port and/or path, store the transit delay for each LAG port to a LAG structure along with an identifier for the LAG port and/or for each path to an equal cost multi-path (ECMP) structure along with an identifier of the path, sort the LAG ports according to each LAG port's transit delay and mark a LAG port having the lowest latency, and sort the paths according to each path's transit delay and mark a path having the lowest latency, wherein each path has an equal path cost factor.

Abstract: In one embodiment, a system for determining latency in paths includes logic integrated with and/or executable by a processor, the logic being adapted to synchronize clocks of two devices connected via two or more link aggregation (LAG) ports and/or multiple devices within paths through a network fabric, determine a transit delay for each LAG port and/or path, store the transit delay for each LAG port to a LAG structure along with an identifier for the LAG port and/or for each path to an equal cost multi-path (ECMP) structure along with an identifier of the path, sort the LAG ports according to each LAG port's transit delay and mark a LAG port having the lowest latency, and sort the paths according to each path's transit delay and mark a path having the lowest latency, wherein each path has an equal path cost factor.