Patents by Inventor Tali KOSINOVSKY

Tali KOSINOVSKY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Internal node jumper for memory bit cells
    Patent number: 11973032
    Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Smita Shridharan, Zheng Guo, Eric A. Karl, George Shchupak, Tali Kosinovsky
  • INTERNAL NODE JUMPER FOR MEMORY BIT CELLS
    Publication number: 20230223339
    Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.
    Type: Application
    Filed: March 8, 2023
    Publication date: July 13, 2023
    Inventors: Smita SHRIDHARAN, Zheng GUO, Eric A. KARL, George SHCHUPAK, Tali KOSINOVSKY
  • Internal node jumper for memory bit cells
    Patent number: 11640939
    Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: May 2, 2023
    Assignee: Intel Corporation
    Inventors: Smita Shridharan, Zheng Guo, Eric A. Karl, George Shchupak, Tali Kosinovsky
  • INTERNAL NODE JUMPER FOR MEMORY BIT CELLS
    Publication number: 20220077055
    Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 10, 2022
    Inventors: Smita SHRIDHARAN, Zheng GUO, Eric A. KARL, George SHCHUPAK, Tali KOSINOVSKY
  • Internal node jumper for memory bit cells
    Patent number: 11205616
    Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Smita Shridharan, Zheng Guo, Eric A. Karl, George Shchupak, Tali Kosinovsky
  • INTERNAL NODE JUMPER FOR MEMORY BIT CELLS
    Publication number: 20200098682
    Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.
    Type: Application
    Filed: June 20, 2017
    Publication date: March 26, 2020
    Inventors: Smita SHRIDHARAN, Zheng GUO, Eric A. KARL, George SHCHUPAK, Tali KOSINOVSKY