Abstract: Fast switching and fast settling is achieved in a phase locked loop (“PLL”) containing a bandwidth switched active loop filter (8) by feeding the phase error signal of the phase detector (1) of the PLL to the non-inverting input of the amplifier (7) within the loop filter and having the electronic switch (17) control the loop filter bandwidth through changing the resistance (9, 11) to ground at the inverting input of the amplifier between a high and low value associated respectively with broad bandwidth and narrow bandwidth to the loop filter. Switching is possible in as little as one microsecond, and is accompanied by fast settling of the loop with minimal generation of phase/frequency perturbation. The foregoing PLL is of particular benefit in fast switching frequency synthesizers, such as used in frequency hopping frequency synthesizers of frequency and time division multiplexing systems.

Abstract: A phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A phase detector (18) is activable in response to a gating signal (20) to generate an error signal representing a difference between a reference frequency signal and the variable output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. An offset cancellation circuit (22) is coupled to the loop filter (12). In response to an error signal representing phase offset of the phase locked loop (10), the offset cancellation circuit (22) supplies a compensating signal to reduce the phase offset.

Abstract: A phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A phase detector (18) is activable in response to a gating signal (20) to generate an error signal representing a difference between a reference frequency signal and the variable output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. An offset cancellation circuit (22) is coupled to the loop filter (12). In response to an error signal representing phase offset of the phase locked loop (10), the offset cancellation circuit (22) supplies a compensating signal to reduce the phase offset.

Abstract: Fast switching and fast settling is achieved in a phase locked loop (“PLL”) containing a bandwidth switched active loop filter (8) by feeding the phase error signal of the phase detector (1) of the PLL to the non-inverting input of the amplifier (7) within the loop filter and having the electronic switch (17) control the loop filter bandwidth through changing the resistance (9, 11) to ground at the inverting input of the amplifier between a high and low value associated respectively with broad bandwidth and narrow bandwidth to the loop filter. Switching is possible in as little as one microsecond, and is accompanied by fast settling of the loop with minimal generation of phase/frequency perturbation. The foregoing PLL is of particular benefit in fast switching frequency synthesizers, such as used in frequency hopping frequency synthesizers of frequency and time division multiplexing systems.