Abstract: The present invention is a method and apparatus to buffer data. A buffer memory of a first type stores data associated with a connection identifier corresponding to a channel in a network. The data is organized into at least one chunk based on a linked list. The connection identifier identifies a connection in the channel. The data is part of a data stream associated with the connection. A packet memory of a second type provides access to the stored data when a transfer condition occurs.

Abstract: The present invention is a method and apparatus to buffer data. A buffer memory of a first type stores data associated with a connection identifier corresponding to a channel in a network. The data is organized into at least one chunk based on a linked list. The connection identifier identifies a connection in the channel. The data is part of a data stream associated with the connection. A packet memory of a second type provides access to the stored data when a transfer condition occurs.

Abstract: The present invention is a method and apparatus to buffer data. A buffer memory of a first type stores data associated with a connection identifier corresponding to a channel in a network. The data is organized into at least one chunk based on a linked list. The connection identifier identifies a connection in the channel. The data is part of a data stream associated with the connection. A packet memory of a second type provides access to the stored data when a transfer condition occurs.

Abstract: A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplier. This input circuitry includes a plurality of Booth recoding logic cells that provide the control signals to multiplexers in the adder cells in the array. The Booth recoding logic cells receive different subsets of bits of the second number and generate the Booth recoded control signals as a function of the received subset of bits. Each Booth recoding logic cell includes balanced logic circuitry for generating all of the Booth recoded control signals from that Booth recoding logic cell at the same time. The balanced logic circuitry minimizes temporary short-circuit paths in the multiplexers in the adder cells. The input circuitry also includes a split bus that provides the first number to the array.

Abstract: A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplier. This input circuitry includes a plurality of Booth recoding logic cells that provide the control signals to multiplexers in the adder cells in the array. The Booth recoding logic cells receive different subsets of bits of the second number and generate the Booth recoded control signals as a function of the received subset of bits. Each Booth recoding logic cell includes balanced logic circuitry for generating all of the Booth recoded control signals from that Booth recoding logic cell at the same time. The balanced logic circuitry minimizes temporary short-circuit paths in the multiplexers in the adder cells. The input circuitry also includes a split bus that provides the first number to the array.

Abstract: An asynchronous pipeline that is divided into separate data and signal chains by moving the data register load signal buffer outside of the closed loop that generates the output request event from the input request event, causing the output request event to occur before output data is available. Matched delays between adjacent pipeline stages permit data and signals to move from stage to stage without problem. Matched delays between stages are possible if: (1) every stage has the same loading; (2) logically adjacent stages are physically located next to each other; (3) the buffered data register load signal has enough drive to latch data reliably; and (4) the delay from input request event to output request event is greater than the latch time of the data register. Input and output circuits transform the internal signals of the pipeline to the correct asynchronous signals for asynchronous source and destination devices or to the correct synchronous signals for synchronous source and destination devices.

Abstract: A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplier. This input circuitry includes a plurality of Booth recoding logic cells that provide the control signals to multiplexers in the adder cells in the array. The Booth recoding logic cells receive different subsets of bits of the second number and generate the Booth recoded control signals as a function of the received subset of bits. Each Booth recoding logic cell includes balanced logic circuitry for generating all of the Booth recoded control signals from that Booth recoding logic cell at the same time. The balanced logic circuitry minimizes temporary short-circuit paths in the multiplexers in the adder cells. The input circuitry also includes a split bus that provides the first number to the array.

Abstract: A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into and out of the registers. Each control cell includes interconnected first and second latches. The first latch receives a request-in signal from a previous control cell and in response produces an intermediate signal. The second latch receives the intermediate signal and in response supplies a request-out signal to a subsequent control cell. The control cell also has a logic circuit coupled to the queue register and first and second latches. In response to input signals, the logic circuit produces load and hold control signals to the queue register and first and second latches. The device includes two-to-four and four-to-two cycle converters that allow the two-cycle FIFO device to be used in either a two-cycle or a four-cycle environment.

Abstract: A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in rows and produces addition results of bits from the first and second numbers. A carry lookahead circuit is coupled to a right side of the array to receive a portion of the addition results and produce the least significant bits of the product. A total delay through the carry lookahead circuit is equal to a total delay through the array of adder cells. A pipeline latch is provided for latching the least significant bits of the product and the addition results from a bottom row of the array of adder cells. An output adder receives the latched addition results of the adder cells of the bottom row and generates the most significant bits of the product.

Abstract: A barrel shifter for shifting a plurality of bits in a single clock cycle has a bypass circuit through which unshifted results from an arithmetic logic unit (ALU) are bypassed around a shift circuit and provided directly to an output of the barrel shifter. An isolation circuit having tristate inverters isolates the shift circuit of the barrel shifter from the ALU results when the results are not to be shifted so that internal signal nodes of the shift circuit with high capacitance will not be switched. When the results are to be shifted, the tristate inverters of the isolation circuit are enabled to pass the results to the shift circuit where they are shifted and then provided to the barrel shifter output. By providing the results to the shift circuit only when a shift is to be performed, and otherwise isolating the shift circuit, power consumption is reduced.

Abstract: A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into and out of the registers. Each control cell includes interconnected first and second latches. The first latch receives a request-in signal from a previous control cell and in response produces an intermediate signal. The second latch receives the intermediate signal and in response supplies a request-out signal to a subsequent control cell. The control cell also has a logic circuit coupled to the queue register and first and second latches. In response to input signals, the logic circuit produces load and hold control signals to the queue register and first and second latches. The device includes two-to-four and four-to-two cycle converters that allow the two-cycle FIFO device to be used in either a two-cycle or a four-cycle environment.