Patents by Inventor Tam T. Do

Tam T. Do has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware-implemented hypervisor for root-of-trust monitoring and control of computer system
    Patent number: 8458791
    Abstract: A system and method for modifying a processor system with hypervisor hardware to provide protection against malware. The processor system is assumed to be of a type having at least a CPU and a high-speed bus for providing data links between the CPU, other bus masters, and peripherals (including a debug interface unit). The hypervisor hardware elements are (1) a co-processor programmed to perform one or more security tasks; (2) a communications interface between the co-processor and the debug interface unit; (3) a behavioral interface on the high-speed bus, configured to monitor control signals from the CPU, and (4) an access controller on the high-speed bus, configured to store access control data, to intercept requests on the high-speed bus, to evaluate the requests against the access control data, and to grant or deny the requests.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: June 4, 2013
    Assignee: Southwest Research Institute
    Inventors: Tam T Do, Michael D LeMay, Galen A Rasche, Ben A Abbott
  • Hardware-Implemented Hypervisor for Root-of-Trust Monitoring and Control of Computer System
    Publication number: 20120047576
    Abstract: A system and method for modifying a processor system with hypervisor hardware to provide protection against malware. The processor system is assumed to be of a type having at least a CPU and a high-speed bus for providing data links between the CPU, other bus masters, and peripherals (including a debug interface unit). The hypervisor hardware elements are (1) a co-processor programmed to perform one or more security tasks; (2) a communications interface between the co-processor and the debug interface unit; (3) a behavioral interface on the high-speed bus, configured to monitor control signals from the CPU, and (4) an access controller on the high-speed bus, configured to store access control data, to intercept requests on the high-speed bus, to evaluate the requests against the access control data, and to grant or deny the requests.
    Type: Application
    Filed: August 18, 2010
    Publication date: February 23, 2012
    Applicant: SOUTHWEST RESEARCH INSTITUTE
    Inventors: Tam T. Do, Michael D. LaMay, Galen A. Rasche, Ben A. Abbott