Abstract: A process monitor test chip and methodology allows process-related manufacturing defects to be quickly identified and isolated. A basic circuit block of a test chip having a number of inverter cells serially connected with a corresponding number of observation points before the input of each inverter cell provides for the inverter cells in the basic circuit block to be probed and thus observed by e-beam technology. Any required number of basic circuit blocks may be serially connected end to end to constitute a chain circuit. Within the test chip itself, a plurality of chain circuits may be connected serially or in parallel to accomplish different testing goals. By controlling an input signal and a control signal of a multiplexing element associated with each chain circuit, the plurality of chain circuits can be forced into a serial connection or a parallel connection.

Abstract: According to the present invention, the functionality and possible process-related defects of an integrated circuit device are quickly assessed and isolated using a special testing methodology. Utilizing a test chip, an Electron Beam (E-Beam) is used to locate defective circuitry of the integrated circuit at functional levels, and an emission microscope is used to locate possible DC leakage related to silicon which is indicative of process-related defects. Using the methodology of the present invention on a test chip rather than a real production device means that the functional analysis time may be reduced from weeks to less than one hour.

Abstract: A method of analyzing an integrated circuit to determine the cause of an open or resistive intermetal via is disclosed. Instead of conventional cross-sectioning of the suspected via, the method removes the upper of the metal layers at the location of the via, with a selective etch to maintain the presence of the contaminant or other cause of failure at the via. When an isotropic metal etch is used, as is preferred, partial removal of the interlevel dielectric layer will facilitate subsequent analysis by increasing the area to be analyzed. Optical microscopy, SEM microscopy, Auger spectroscopy, EDS spectroscopy, and other conventional analysis techniques may be used at the portion of the circuit within the failed via, to indicate the composition of the undesired contaminant.