Abstract: According to one embodiment, an automatic analyzing apparatus includes a probe and a liquid level detector. The liquid level detector is electrically connected to the probe and detects contact between the probe and a liquid surface, wherein the liquid level detector comprises an adjuster configured to adjust electrostatic capacitance of one or more capacitors for circuitry for use in liquid level detection.

Abstract: According to one embodiment, an automatic analyzing apparatus includes a probe and a liquid level detector. The liquid level detector is electrically connected to the probe and detects contact between the probe and a liquid surface, wherein the liquid level detector comprises an adjuster configured to adjust electrostatic capacitance of one or more capacitors for circuitry for use in liquid level detection.

Abstract: A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

Abstract: A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

Abstract: A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

Abstract: A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

Abstract: An interference canceling device comprising a flat phase IF narrow band BPF. A signal which has been branched from a signal on the main line is filtered by the BPF and is recombined with the signal on the main line. Phase rotation caused by frequency separation from the pass band center frequency does not occur because the phase characteristics of the BPF are substantially flat in the pass band. Thus, interference existing not only in a pin-point frequency, but over a band of frequencies can be cancelled.

Abstract: A circuit for biasing an FET, comparing a gate bias voltage of the FET with a reference voltage at an operational amplifier and performing closed-loop control on the gate bias voltage of the FET with the output of the operational amplifier. The temperature characteristics of the mutual conductance of the FET is compensated by setting the temperature characteristics of one or both of two voltage dividing resistors. Variations in a drain bias current due to input signal level and temperature changes can be suppressed. The circuit at the gate and the circuit at the drain are separate, making possible class A, class AB, and class B operations. The voltage drop at the gate resistor can be ignored so that the gate resistor can be designed with priority given to stability of the RF characteristics.

Abstract: A circuit for biasing an FET, comparing a gate bias voltage of the FET with a reference voltage at an operational amplifier and performing closed-loop control on the gate bias voltage of the FET with the output of the operational amplifier. The temperature characteristics of the mutual conductance of the FET is compensated by setting the temperature characteristics of one or both of two voltage dividing resistors. Variations in a drain bias current due to input signal level and temperature changes can be suppressed. The circuit at the gate and the circuit at the drain are separate, making possible class A, class AB, and class B operations. The voltage drop at the gate resistor can be ignored so that the gate resistor can be designed with priority given to stability of the RF characteristics.