Abstract: In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.

Abstract: In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.

Abstract: A precharge signal generation circuit outputs a precharge signal including a pulse every access cycle with respect to a data register in a first mode, and generates a precharge signal by masking the signal including the pulse every access cycle with respect to the data register when access to a memory cell other than a predetermined memory cell in the data register is designated in a second mode. A first precharge circuit precharges a bit line pair in response to activation of the precharge signal.

Abstract: A precharge signal generation circuit outputs a precharge signal including a pulse every access cycle with respect to a data register in a first mode, and generates a precharge signal by masking the signal including the pulse every access cycle with respect to the data register when access to a memory cell other than a predetermined memory cell in the data register is designated in a second mode. A first precharge circuit precharges a bit line pair in response to activation of the precharge signal.

Abstract: A semiconductor memory device is of a bank switching type having a plurality of memory array banks provided in a memory chip which can be switched from one to another for storage operation. The semiconductor memory device includes: a plurality of memory arrays in the memory array banks; an input/output circuit for transmitting information data between the memory arrays and the outside; a data bus for connecting between the memory arrays and the input/output circuit; and N-channel transistors provided across the data bus. The data bus consists of a plurality of adjacent lines. Each of N-channel transistors is connected at their drain to the corresponding lines of the data bus while at their source to the ground. When a multi-bit test is commenced for writing and reading data on the memory arrays, the N-channel transistors are turned on to connect the lines of the data bus to the ground.

Abstract: The state of a prescribed internal column address signal bit is selectively fixed according to a mode switch circuit. A specific row address signal bit is transmitted instead of a column address signal bit under the control of the mode switch circuit. Thus, a semiconductor memory device having a plurality of storage capacities and address spaces is realized with a single chip structure.

Abstract: A semiconductor memory device is of a bank switching type having a plurality of memory array banks provided in a memory chip which can be switched from one to another for storage operation. The semiconductor memory device includes: a plurality of memory arrays in the memory array banks; an input/output circuit for transmitting information data between the memory arrays and the outside; a data bus for connecting between the memory arrays and the input/output circuit; and N-channel transistors provided across the data bus. The data bus consists of a plurality of adjacent lines. Each of N-channel transistors is connected at their drain to the corresponding lines of the data bus while at their source to the ground. When a multi-bit test is commenced for writing and reading data on the memory arrays, the N-channel transistors are turned on to connect the lines of the data bus to the ground.

Abstract: The state of a prescribed internal column address signal bit is selectively fixed according to a mode switch circuit. A specific row address signal bit is transmitted instead of a column address signal bit under the control of the mode switch circuit. Thus, a semiconductor memory device having a plurality of storage capacities and address spaces is realized with a single chip structure.

Abstract: A plurality of vending machines are connected via a radio network to a main computer. A common electronic mail address is allocated to these vending machines. A unique identification number ID is allocated to each vending machine. The vending machine transmits electronic mails regularly and at the time of request for replenishment. The main computer manages sales status of each vending machine according to an identification number included in an electronic mail.