Patents by Inventor Tamao Takase

Tamao Takase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6555925
    Abstract: The present invention is a method of producing a semiconductor device in which at least one alignment mark to be used in an exposure process of a lithographic process is formed of a wiring material which is copper or includes copper as a main component, and the alignment mark is formed entirely in an area outside an area where dicing is to be executed.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: April 29, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tamao Takase, Hisashi Kaneko, Hideki Shibata
  • Patent number: 6541861
    Abstract: A semiconductor manufacturing method has the steps of preparing an SOI substrate having a supporting substrate, an insulating film formed above the supporting substrate, a semiconductor region formed above the insulating film, and an intermediate layer formed between the supporting substrate and the insulating film, forming a semiconductor element in the semiconductor region, and removing the intermediate layer to separate the supporting substrate and the semiconductor region in which the semiconductor element is formed.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: April 1, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki Higashi, Tamao Takase, Hideki Shibata
  • Publication number: 20020011670
    Abstract: A semiconductor manufacturing method has the steps of preparing an SOI substrate having a supporting substrate, an insulating film formed above the supporting substrate, a semiconductor region formed above the insulating film, and an intermediate layer formed between the supporting substrate and the insulating film, forming a semiconductor element in the semiconductor region, and removing the intermediate layer to separate the supporting substrate and the semiconductor region in which the semiconductor element is formed.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 31, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuyuki Higashi, Tamao Takase, Hideki Shibata
  • Patent number: 6051508
    Abstract: The present invention intends to form multilayer interconnects without deteriorating the advantage of an organosiloxane film (an interlayer dielectric), i.e., the low dielectric constant. According to the present invention, an organosiloxane film, a silicon nitride film, an inorganic SOG film, and a photoresist pattern are formed on a first metal layer, in series. The inorganic SOG film is then etched with use of the photoresist pattern as a mask to transfer the photoresist pattern to the inorganic SOG film. The photoresist pattern is then removed by oxygen plasma treatment with use of the silicon nitride film as a protection mask for protecting the organosiloxane film. Subsequently thereto, the silicon nitride film and the organosiloxane film are etched with use of the inorganic SOG film to form a contact hole reaching the first metal layer. After removing the inorganic SOG film, a second metal layer is formed to contact with the first metal layer through the contact hole.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: April 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tamao Takase, Tadashi Matsuno, Hideshi Miyajima