Abstract: Components and processes are disclosed herein for managing non-volatile and/or low-volatility byproduct materials that are generated within a plasma processing region of a plasma processing chamber during performance of various plasma-based processes on a substrate. The components include a top window structure, a liner structure, an edge ring structure, a focus ring structure, a ground ring structure, a substrate access port shield, an insert liner for a port opening in a chamber wall, and an exhaust baffle assembly for positioning within an exhaust channel connected to the chamber. One or more process-exposed surface(s) of the various components are subjected to a surface roughening/texturizing process to impart a surface roughness and/or engineered topography to the process-exposed surface that promotes adhesion and retention of plasma process byproduct materials.

Abstract: An edge ring assembly is provided, including: an upper edge ring configured to surround an electrostatic chuck (ESC), the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface, the upper edge ring being disposed above the annular shelf; a lower inner edge ring disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower inner edge ring being defined from an electrically conductive material, the lower inner edge ring being electrically insulated from the ESC; a lower outer edge ring surrounding the inner edge ring, the lower outer edge ring being disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower outer edge ring being defined from an electrically insulating material.

Abstract: An edge ring assembly is provided, including: an upper edge ring configured to surround an electrostatic chuck (ESC), the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface, the upper edge ring being disposed above the annular shelf; a lower inner edge ring disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower inner edge ring being defined from an electrically conductive material, the lower inner edge ring being electrically insulated from the ESC; a lower outer edge ring surrounding the inner edge ring, the lower outer edge ring being disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower outer edge ring being defined from an electrically insulating material.

Abstract: A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.

Abstract: A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.

Abstract: A method for etching a substrate having a silicon layer in a plasma processing chamber having a bottom electrode on which the substrate is disposed on during etching. The method includes performing a main etch step. The method also includes terminating main etch step when a predefined etch depth of at least 70 percent of thickness into silicon layer is achieved. The method further includes performing an overetch step. The overetch step including a first process step and a second process step. First process step is performed using a first bottom power level applied to bottom electrode. Second process step is performed using a second bottom power level applied to bottom electrode that is lower than first bottom power level. First process and second process steps are alternately performed a plurality of times. The method yet also includes terminating overetch step after silicon layer is etched through.

Abstract: A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.

Abstract: In a plasma processing system, a method for optimizing etching of a substrate is disclosed. The method includes selecting a first plasma process recipe including a first process variable, wherein changing the first process variable by a first amount optimizes a first substrate etch characteristic and aggravates a second substrate etch characteristic. The method also includes selecting second plasma process recipe including a second process variable, wherein changing the second process variable by a second amount aggravates the first substrate etch characteristic and optimizes the second substrate etch characteristic. The method further includes positioning a substrate on a chuck in a plasma processing chamber; and striking a plasma within the plasma processing chamber.

Abstract: A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch step, which includes a first, second, and third process steps. The first process step employs a first process recipe, the second process step employs a second process recipe, and the third process step employs a third process recipe. The second process recipe employs a second bottom bias voltage level applied to the bottom electrode which is higher than the first bottom bias voltage level employs in the first process recipe and the third bottom bias voltage level employs in the third process recipe. The first, second, and third process steps are alternated a plurality of times until silicon layer is etched through.

Abstract: A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch step, which includes a first, second, and third process steps. The first process step employs a first process recipe, the second process step employs a second process recipe, and the third process step employs a third process recipe. The second process recipe employs a second bottom bias voltage level applied to the bottom electrode which is higher than the first bottom bias voltage level employs in the first process recipe and the third bottom bias voltage level employs in the third process recipe. The first, second, and third process steps are alternated a plurality of times until silicon layer is etched through.

Abstract: A method for etching a substrate having a silicon layer in a plasma processing chamber having a bottom electrode on which the substrate is disposed on during etching. The method includes performing a main etch step. The method also includes terminating main etch step when a predefined etch depth of at least 70 percent of thickness into silicon layer is achieved. The method further includes performing an overetch step. The overetch step including a first process step and a second process step. First process step is performed using a first bottom power level applied to bottom electrode. Second process step is performed using a second bottom power level applied to bottom electrode that is lower than first bottom power level. First process and second process steps are alternately performed a plurality of times. The method yet also includes terminating overetch step after silicon layer is etched through.

Abstract: In a plasma processing system, a method for optimizing etching of a substrate is disclosed. The method includes selecting a first plasma process recipe including a first process variable, wherein changing the first process variable by a first amount optimizes a first substrate etch characteristic and aggravates a second substrate etch characteristic. The method also includes selecting second plasma process recipe including a second process variable, wherein changing the second process variable by a second amount aggravates the first substrate etch characteristic and optimizes the second substrate etch characteristic. The method further includes positioning a substrate on a chuck in a plasma processing chamber; and striking a plasma within the plasma processing chamber.

Abstract: The present invention provides methods of processing a substrate with minimal scalloping. By processing substrates with minimal scalloping, feature tolerance and quality may be improved. An embodiment of the present invention provides a method for etching a feature in a layer through an etching mask by alternating steps of polymer deposition and substrate etching in any order. In order to achieve the benefits described herein, process gas pressures between process steps may be substantially equivalent. In some embodiments a continuous plasma stream may be maintained throughout substrate processing. In still other embodiments, process gases may be controlled by a single mass flow control valve so that process gases may be switched to within less than 250 milliseconds.

Abstract: A method of plasma etching of silicon that utilizes the plasma to provide laterally defined recess structures through a mask. The method is based on the variation of the plasma parameters to provide a well-controlled anisotropic etch, while achieving a very high etch rate, and a high selectivity with respect to a mask. A mixed gas is introduced into the vacuum chamber after the chamber is evacuated, and plasma is generated within the chamber. The substrate's surface is exposed to the plasma. Power sources are used for formation of the plasma discharge. An integrated control system is used to modulate the plasma discharge power and substrate polarization voltage levels.

Abstract: A method of plasma etching of silicon that utilizes the plasma to provide laterally defined recess structures through a mask. The method is based on the variation of the plasma parameters to provide a well-controlled anisotropic etch, while achieving a very high etch rate, and a high selectivity with respect to a mask. A mixed gas is introduced into the vacuum chamber after the chamber is evacuated, and plasma is generated within the chamber. The substrate's surface is exposed to the plasma. Power sources are used for formation of the plasma discharge. An integrated control system is used to modulate the plasma discharge power and substrate polarization voltage levels.

Abstract: A recessed sputtering target assembly is provided with a bonding material disposed between a dielectric target and a backing plate. The bond line of the bonding material is recessed away from the edges of the target and backing plate, preferably by ¼ inch. The sputtering target assembly may be used during high RF power processes to achieve high deposition rates without arcing of the bonding material or contamination of the sputtering chamber.