Abstract: A current sense/limit circuit senses a current of a power switch and turns off the switch when a peak current of the power switch surpasses a preprogrammed value. To prevent the circuit from reacting to a leading edge current spike resulting from the reverse recovery of a clamp or diode which is a part of most power processing circuits, the current sense/limit circuit monitors the voltage on the power switch and disables the current sense circuitry as long as this voltage does not drop below a predetermined threshold value. The predetermined threshold value is higher than the worst case voltage on the power switch during its on-time under normal operating conditions, and much lower than the switch voltage during off-time. As a result, this method adaptively blocks the current sense mechanism during most of the reverse recovery current spike period.

Abstract: A biasing circuit and method of producing a biasing voltage particularly suitable for integrated circuits combining MOS and bipolar technology. The circuit includes an NMOS transistor which produces a gate-source reference voltage when drain current is supplied to the transistor. The reference gate-source voltage is coupled to the output of the circuit at a reduced impedance level so as to increase noise immunity. The coupling circuit preferably includes two NPN bipolar transistors. The NPN transistors add and subtract identical base-emitter junction voltages to the reference voltage so that the magnitude of the reference voltage is unchanged. An NMOS transistor, having a gate-source voltage equal to the reference voltage, is also connected to the output for reducing the output impedance of the circuit.

Abstract: A current limiting circuit (200, 300, 400) for instantaneously limiting the peak current of a fast high side power switch (212) or power FET has a reference switch (213) or FET, a first comparator (218), a current source I.sub.CL, control circuitry (209), and a clamping circuit (238). The reference FET (213) is smaller than the power FET (212). The first comparator compares the voltage drop across the power FET (212) and compares it with the voltage drop across the reference FET (213) and produces a signal COMPOUT which initiates the turn-off of the power FET (212) if the voltage drop across the power FET (212), caused by a load current flowing through it, is greater than or equal to the reference FET voltage drop induced by I.sub.CL. The clamp circuit (238), having diodes (D.sub.1, D.sub.2) and a tracking current source I'.sub.CL, disconnects the FETS (212, 213) from the comparator (218) when they are OFF.

Abstract: A circuit (20, 40, 50, 60) for generating an optimal compensating ramp voltage signal V.sub.cramp, with the minimum necessary slope, m.sub.c for a current mode DC/DC converter is shown. The adaptive compensating ramp generating circuit (20) is comprised of two voltage dividers (22, 24), the first voltage divider 22 divides an input voltage V.sub.IN and the second voltage divider 24 divides an output voltage V.sub.OUT. The first voltage divider (22) has two resistors (26, 28) in series: the first resistor (26) has a resistance of (1/B-1) * R ohms and the second resistor (28) has a resistance of R ohms. V.sub.OUT is divided by the second voltage divider (24) having two resistors (29, 30) in series: the first resistor (29) has a resistance of (1/A-1) * R ohms and the second resistor (30) has a resistance of R ohms. The constants A, B, and C are selected for the particular type of DC/DC converter employed. The divided voltages A * V.sub.OUT and B * V.sub.IN are input into a voltage controlled current source (32).

Abstract: An hysteretic current-mode controlled DC to DC converter has an input voltage, an output voltage and a control switch. The switch alternately coupled the input voltage into an energy storage inductor. It is controlled by an hysteretic conparater sensing the current of the inductor and having turn-on and turn-off limits. The limits are symmetrical about an average inductor current. The limits are adjusted by simple non-closed-loop methods to maintain an approximately constant frequency of oscillation. The average inductor current is controlled by an error amplifier to maintain a constant output voltage. The two controls are independent.

Abstract: An error amplifier is disclosed for use in linear or switched-mode voltage or current regulators that use a transconductance type power-amplifier, enabling easy modular parallel connection of said regulators by simply parallel wiring of normally externally accessible nodes of the individual regulators: power-input, power-output, error amplifier output, and error amplifier input, to boost the system's total output power by about equally sharing the total output power among the individual regulators, includinga. an amplifier with grossly asymmetric output current capability in sink and source directions; andb. a sense circuit to slightly modify the voltage on the reference input of the said amplifier when the lower value output current limit becomes active so that it causes positive feedback thereby ensuring that at any time only one of the plurality of parallel operated amplifiers is active and controls the system's output while all the other amplifiers are in current limit and thereby inactive.

Abstract: A PWM-FM control method and circuit is employed to control the output level of a resonant switch-mode inverter/converter. The frequency of the inverter/converter is controlled via a nonlinear function shaper and VCO or ICO by the same voltage which controls the pulse-width such that the turn-on of the controlled switching element(s) always occur(s) at substantially zero voltage and substantially zero current across the switching element(s), thereby minimizing switching losses and maximizing efficiency.

Abstract: A speed up circuit for a current mirror is disclosed. The turn on drive current is greatly increased for a brief transient interval. The increased current acts to rapidly charge circuit load capacitance and thereby reduce turn on time.

Abstract: A switching circuit is employed to control the flow of energy from a power source to a tuned load. The control is achieved by means of a pulse width control voltage. The load current is sensed and fed to a phase locked loop which contains an oscillator producing an output that is slightly above load resonance. The phase locked loop forces the circuit to operate at a frequency where the modulating pulses are initiated at the load current zero crossing. The circuit is shown in use in a regulated d-c power supply and in a fluorescent lamp power supply application.