Patents by Inventor Tamer ALI

Tamer ALI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8958501
    Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: February 17, 2015
    Assignee: Broadcom Corporation
    Inventors: Ali Nazemi, Mahmoud Reza Ahmadi, Tamer Ali, Bo Zhang, Mohammed Abdul-Latif, Namik Kocaman, Afshin Momtaz
  • Publication number: 20140320229
    Abstract: A transmission line driver including an output configured to have a load impedance is provided. The transmission line driver includes a pull-up circuit coupled in series with the output. The transmission line driver also includes a pull-down circuit coupled in series with the output. The transmission line driver includes a shunt circuit having an adjustable impedance. The shunt circuit is coupled in parallel to the output. The shunt circuit is coupled to the pull-up circuit and the pull-down circuit. The shunt circuit is configured to receive a shunt control signal to adjust the adjustable impedance to provide linear control of an output swing at the output.
    Type: Application
    Filed: May 17, 2013
    Publication date: October 30, 2014
    Applicant: Broadcom Corporation
    Inventor: Tamer ALI
  • Publication number: 20140241442
    Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.
    Type: Application
    Filed: July 19, 2013
    Publication date: August 28, 2014
    Inventors: Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Ali, Ali Nazemi, Hassan Maarefi, Burak Catli, Afshin Momtaz
  • Publication number: 20140146922
    Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.
    Type: Application
    Filed: December 19, 2012
    Publication date: May 29, 2014
    Applicant: BROADCOM CORPORATION
    Inventors: Ali Nazemi, Mahmoud Reza Ahmadi, Tamer Ali, Bo Zhang, Mohammed Abdul-Latif, Namik Kocaman, Afshin Momtaz
  • Patent number: 8664973
    Abstract: Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: March 4, 2014
    Assignee: Broadcom Corporation
    Inventors: Tamer Ali, Ali Nazemi
  • Publication number: 20140036982
    Abstract: Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: Broadcom Corporation
    Inventors: Tamer ALI, Ali Nazemi, Namik Kocaman
  • Publication number: 20140035696
    Abstract: Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: Broadcom Corporation
    Inventors: Tamer ALI, Ali Nazemi
  • Patent number: 7292075
    Abstract: A pad driver is presented that in one form is capable of driving a wide range of capacitive loads with constant rise and fall times, over a wide range of temperature and process corners. A desirable form of the pad driver is characterized by the ability to charge and discharge rail-to-rail with a constant charging and discharging rate over the whole charging and discharging cycles. Furthermore, desirably the driver is independent of any load present at the output pad.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: November 6, 2007
    Inventors: Ahmed Kamal Abdel-Hamid, Tamer Ali Abdel-Rahim