Abstract: A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.

Abstract: A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal.

Abstract: A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.

Abstract: A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.

Abstract: A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.

Abstract: A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal.