Patents by Inventor Tamer Mohammed Ali
Tamer Mohammed Ali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146269Abstract: A differential all-pass coupling circuit with common mode feedback is disclosed. An example apparatus includes an anti-aliasing circuit configured to reduce a bandwidth of a first differential signal, and a switched-capacitor circuit coupled to the anti-aliasing circuit configured to control a first switch to charge a capacitor to a first voltage based on a first difference between (i) a common mode input voltage associated with a first common mode voltage of the first differential signal and (ii) a common mode reference voltage associated with a second common mode voltage of an input stage of the receiver, control a second switch to provide a second voltage to the capacitor based on a second difference between the first differential signal and the common mode input voltage, and output a second differential signal to the input stage based on the first differential signal adjusted by the second voltage.Type: ApplicationFiled: September 28, 2023Publication date: May 2, 2024Applicant: MediaTek Inc.Inventors: Ahmed Othman Mohamed Mohamed ElShater, Ramy Awad, Tamer Mohammed Ali
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Publication number: 20240146326Abstract: The techniques described herein relate to analog-assisted feed-forward equalizers. An example apparatus includes a first charge element digital-to-analog converter (DAC) including a first plurality of charge storage elements configured to store first samples of charge based on respective first portions of a digital input signal, and generate, based on the first samples, a first analog output signal proportional to the first portions. The apparatus further includes a second charge element DAC coupled to the first charge element DAC and including a second plurality of charge storage elements configured to store second samples of charge based on respective second portions of the digital input signal, and generate, based on the second samples, a second analog output signal proportional to the second portions, and wherein the coupling of the first and second outputs generates a third analog output signal based on a combination of the first and second analog output signals.Type: ApplicationFiled: September 28, 2023Publication date: May 2, 2024Applicant: Media Tek Inc.Inventors: Ahmed Safwat Mohamed Aboelenein Elmallah, Amed Othman Mohamed Mohamed ElShater, Tamer Mohammed Ali
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Patent number: 11923819Abstract: Disclosed herein are embodiments of a wide bandwidth attenuator circuit having a tunable gain and tunable input impedance. In some embodiments, the wideband attenuator circuit comprises a serial capacitor shunted to ground by a plurality of circuit slices that are connected in parallel and switchably coupled to the output node of the attenuator. Each circuit slice has a tunable resistor that can be set to a conductive state (“enabled”) or a high impedance state (“disabled”) The number of enabled circuit slices that are connected in parallel may be used to program the attenuator gain and the attenuator impedance.Type: GrantFiled: May 13, 2022Date of Patent: March 5, 2024Assignee: MEDIATEK Singapore Pte. Ltd.Inventors: Henry Arnold Park, Tamer Mohammed Ali
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Patent number: 11894956Abstract: A continuous time linear equalizer (CTLE) includes a first circuit path having a step response that increases from an first initial value to a steady state value higher than the first initial value. The CTLE also includes a second circuit path in parallel with the first circuit path, the second circuit path having a step response that increases from a second initial value to a peak and subsequently falls to second steady state value that is approximately equal to the second initial value. The CTLE is configured to combine an output of the first circuit path and an output of the second circuit path.Type: GrantFiled: February 18, 2022Date of Patent: February 6, 2024Assignee: MEDIATEK Singapore Pte. Ltd.Inventors: Henry Arnold Park, Qaiser Nehal, Tamer Mohammed Ali
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Publication number: 20230025012Abstract: A continuous time linear equalizer (CTLE) includes a first circuit path having a step response that increases from an first initial value to a steady state value higher than the first initial value. The CTLE also includes a second circuit path in parallel with the first circuit path, the second circuit path having a step response that increases from a second initial value to a peak and subsequently falls to second steady state value that is approximately equal to the second initial value. The CTLE is configured to combine an output of the first circuit path and an output of the second circuit path.Type: ApplicationFiled: February 18, 2022Publication date: January 26, 2023Applicant: Media Tek Singapore Pte. Ltd.Inventors: Henry Arnold Park, Qaiser Nehal, Tamer Mohammed Ali
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Patent number: 11552830Abstract: A low power receiver having a feedforward equalization, FFE, based continuous time linear equalizer, CTLE. The FFE CTLE comprises: an input for receiving an input signal; a main first path operably coupled to the input and comprising a source-follower transistor arranged to apply a scaling factor to the received input signal; a second path operably coupled to the input and comprising a delay arranged to apply a delay to the received input signal and a common source transistor common source transistor arranged to apply a scaling factor to the received delayed input signal, wherein the source-follower transistor and the common source, CS, transistor are connected as a single SF-CS stage whose output is arranged to subtract the output of the common source transistor from an output of the source-follower transistor.Type: GrantFiled: September 23, 2021Date of Patent: January 10, 2023Assignee: MediaTek Singapore Pte. LtdInventors: Ahmed Othman Mohamed ElShater, Ramy Awad, Tamer Mohammed Ali
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Publication number: 20220407490Abstract: Disclosed herein are embodiments of a wide bandwidth attenuator circuit having a tunable gain and tunable input impedance. In some embodiments, the wideband attenuator circuit comprises a serial capacitor shunted to ground by a plurality of circuit slices that are connected in parallel and switchably coupled to the output node of the attenuator. Each circuit slice has a tunable resistor that can be set to a conductive state (“enabled”) or a high impedance state (“disabled”) The number of enabled circuit slices that are connected in parallel may be used to program the attenuator gain and the attenuator impedance.Type: ApplicationFiled: May 13, 2022Publication date: December 22, 2022Applicant: MEDIATEK Singapore Pte. Ltd.Inventors: Henry Arnold Park, Tamer Mohammed Ali
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Patent number: 11469729Abstract: A receiver front-end includes a first variable-gain amplifier that performs attenuation; a continuous time linear equalizer coupled to the input or output of the first variable-gain amplifier, wherein a combination of the first variable-gain amplifier and the continuous time linear equalizer produces a processed signal; a plurality of track-and-hold circuits that sample the processed signal in an interleaved manner; and a plurality of second variable-gain amplifiers receiving input signals from the plurality of track-and-hold circuits respectively.Type: GrantFiled: May 11, 2020Date of Patent: October 11, 2022Assignee: MEDIATEK Singapore Pte. Ltd.Inventors: Ramy Awad, Tamer Mohammed Ali, E-Hung Chen, Miguel Francisco Gandara
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Publication number: 20220103400Abstract: A low power receiver having a feedforward equalization, FFE, based continuous time linear equalizer, CTLE. The FFE CTLE comprises: an input for receiving an input signal; a main first path operably coupled to the input and comprising a source-follower transistor arranged to apply a scaling factor to the received input signal; a second path operably coupled to the input and comprising a delay arranged to apply a delay to the received input signal and a common source transistor common source transistor arranged to apply a scaling factor to the received delayed input signal, wherein the source-follower transistor and the common source, CS, transistor are connected as a single SF-CS stage whose output is arranged to subtract the output of the common source transistor from an output of the source-follower transistor.Type: ApplicationFiled: September 23, 2021Publication date: March 31, 2022Inventors: Ahmed Othman Mohamed ElShater, Ramy Awad, Tamer Mohammed Ali
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Patent number: 11221379Abstract: Systems and methods for detecting the presence and/or location of defects (e.g., incomplete solders, broken cables, misconnections, defective sockets, opens, shorts, etc.) along electrical lines are described. The systems and methods described herein may use time-domain reflectometry (TDR), a measurement technique used to determine the characteristics of electrical lines by observing reflected waveforms. TDR may be performed in some embodiments by determining the times when a first event and a second event occur, and by determining the space traveled by a probe signal based on these times. The first event may occur when a first signal transition crosses a first threshold and the second event may occur when a second signal transition crosses a second threshold, where the second signal transition may arise in response to the first signal transition reflecting against a defect along the electrical line.Type: GrantFiled: April 10, 2020Date of Patent: January 11, 2022Assignee: MEDIATEK Singapore Pte. Ltd.Inventors: Huan-Sheng Chen, Henry Arnold Park, Tamer Mohammed Ali
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Patent number: 11025240Abstract: Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.Type: GrantFiled: August 8, 2017Date of Patent: June 1, 2021Assignee: MediaTek Inc.Inventors: Henry Arnold Park, Tamer Mohammed Ali
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Publication number: 20200395909Abstract: A receiver front-end includes a first variable-gain amplifier that performs attenuation; a continuous time linear equalizer coupled to the input or output of the first variable-gain amplifier, wherein a combination of the first variable-gain amplifier and the continuous time linear equalizer produces a processed signal; a plurality of track-and-hold circuits that sample the processed signal in an interleaved manner; and a plurality of second variable-gain amplifiers receiving input signals from the plurality of track-and-hold circuits respectively.Type: ApplicationFiled: May 11, 2020Publication date: December 17, 2020Applicant: MEDIATEK Singapore Pte. LtdInventors: Ramy Awad, Tamer Mohammed Ali, E-Hung Chen, Miguel Francisco Gandara
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Patent number: 10804924Abstract: System for reducing pattern-dependent inter-symbol interference (ISI) are described. These systems may be implemented using complementary metal-oxide-semiconductor (CMOS) transistors. These systems are designed to clamp the voltage propagating along the datapath to a value that is a fraction of the supply voltage. Furthermore, these systems are designed to reduce the time constant of the datapath. One such system comprises a source including a digital-to-analog converter (DAC) and a destination comprising an analog-to-digital converter (ADC). A circuit disposed along the data path from the DAC to the ADC is configured to receive a supply voltage, receive an input signal from the DAC, and produce an output signal based on the input signal by clamping the output signal to a voltage that is a fraction of the supply voltage.Type: GrantFiled: September 23, 2019Date of Patent: October 13, 2020Assignee: MEDIA TEK Singapore Pte. Ltd.Inventors: Henry Arnold Park, Tamer Mohammed Ali
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Publication number: 20200309864Abstract: Systems and methods for detecting the presence and/or location of defects (e.g., incomplete solders, broken cables, misconnections, defective sockets, opens, shorts, etc.) along electrical lines are described. The systems and methods described herein may use time-domain reflectometry (TDR), a measurement technique used to determine the characteristics of electrical lines by observing reflected waveforms. TDR may be performed in some embodiments by determining the times when a first event and a second event occur, and by determining the space traveled by a probe signal based on these times. The first event may occur when a first signal transition crosses a first threshold and the second event may occur when a second signal transition crosses a second threshold, where the second signal transition may arise in response to the first signal transition reflecting against a defect along the electrical line.Type: ApplicationFiled: April 10, 2020Publication date: October 1, 2020Applicant: MEDIATEK Singapore Pte. Ltd.Inventors: Huan-Sheng Chen, Henry Arnold Park, Tamer Mohammed Ali
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Patent number: 10732215Abstract: Systems and methods for detecting the presence and/or location of defects (e.g., incomplete solders, broken cables, misconnections, defective sockets, opens, shorts, etc.) along electrical lines are described. The systems and methods described herein may use time-domain reflectometry (TDR), a measurement technique used to determine the characteristics of electrical lines by observing reflected waveforms. TDR may be performed in some embodiments by determining the times when a first event and a second event occur, and by determining the space traveled by a probe signal based on these times. The first event may occur when a first signal transition crosses a first threshold and the second event may occur when a second signal transition crosses a second threshold, where the second signal transition may arise in response to the first signal transition reflecting against a defect along the electrical line.Type: GrantFiled: June 4, 2018Date of Patent: August 4, 2020Assignee: MEDIATEK Singapore Pte. Ltd.Inventors: Henry Arnold Park, Tamer Mohammed Ali, Shih-Hao Huang, Chien-Hua Wu
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Publication number: 20200244280Abstract: System for reducing pattern-dependent inter-symbol interference (ISI) are described. These systems may be implemented using complementary metal-oxide-semiconductor (CMOS) transistors. These systems are designed to clamp the voltage propagating along the datapath to a value that is a fraction of the supply voltage. Furthermore, these systems are designed to reduce the time constant of the datapath. One such system comprises a source including a digital-to-analog converter (DAC) and a destination comprising an analog-to-digital converter (ADC). A circuit disposed along the data path from the DAC to the ADC is configured to receive a supply voltage, receive an input signal from the DAC, and produce an output signal based on the input signal by clamping the output signal to a voltage that is a fraction of the supply voltage.Type: ApplicationFiled: September 23, 2019Publication date: July 30, 2020Applicant: MEDIATEK Singapore Pte. Ltd.Inventors: Henry Arnold Park, Tamer Mohammed Ali
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Patent number: 10651825Abstract: An attenuator system comprising a variable impedance configured to provide an impedance from among a plurality of impedance states, the variable impedance comprising a first port, a second port, a first transistor comprising first and second channel terminals coupled between the first port and the second port, and a second transistor comprising first and second channel terminals coupled between the first port and the second port, and a control circuit configured to control the variable impedance to a first impedance state of the plurality of impedance states at least in part by providing a first output voltage to a control terminal of the first transistor to turn the first transistor on, wherein the first transistor is configured to operate in an under-driven mode when turned on.Type: GrantFiled: March 22, 2019Date of Patent: May 12, 2020Assignee: MEDIATEK Singapore Pte. Ltd.Inventors: E-Hung Chen, Tamer Mohammed Ali, Ahmed Othman Mohamed Mohamed ElShater, Mazen Soliman Shawky Soliman
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Publication number: 20190305758Abstract: An attenuator system comprising a variable impedance configured to provide an impedance from among a plurality of impedance states, the variable impedance comprising a first port, a second port, a first transistor comprising first and second channel terminals coupled between the first port and the second port, and a second transistor comprising first and second channel terminals coupled between the first port and the second port, and a control circuit configured to control the variable impedance to a first impedance state of the plurality of impedance states at least in part by providing a first output voltage to a control terminal of the first transistor to turn the first transistor on, wherein the first transistor is configured to operate in an under-driven mode when turned on.Type: ApplicationFiled: March 22, 2019Publication date: October 3, 2019Applicant: MEDIATEK Singapore Pte. Ltd.Inventors: E-Hung Chen, Tamer Mohammed Ali, Ahmed Othman Mohamed Mohamed ElShater, Mazen Soliman Shawky Soliman
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Publication number: 20190304899Abstract: Systems and method for supply noise suppression in electronic circuits are described. The systems described herein may prevent or at least limit noise coupling from a supply line to a load, and may further prevent or at least limit noise generated at the load from coupling to the supply line. The systems and methods described herein may be particularly useful in systems-on-chip with multi-level interposers, in which multiple supply lines are used to provide different voltage levels to the chip. In these systems, in fact, the supply lines can exhibit large impedances, which may in turn promote noise coupling from one circuit to another. In one example, a voltage regulator is provided that includes a linear regulator and an active shunt circuit.Type: ApplicationFiled: December 12, 2018Publication date: October 3, 2019Applicant: MEDIATEK Singapore Pte. Ltd.Inventors: Henry Arnold Park, Tamer Mohammed Ali, E-Hung Chen, Huan-Sheng Chen
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Publication number: 20190195936Abstract: Systems and methods for detecting the presence and/or location of defects (e.g., incomplete solders, broken cables, misconnections, defective sockets, opens, shorts, etc.) along electrical lines are described. The systems and methods described herein may use time-domain reflectometry (TDR), a measurement technique used to determine the characteristics of electrical lines by observing reflected waveforms. TDR may be performed in some embodiments by determining the times when a first event and a second event occur, and by determining the space traveled by a probe signal based on these times. The first event may occur when a first signal transition crosses a first threshold and the second event may occur when a second signal transition crosses a second threshold, where the second signal transition may arise in response to the first signal transition reflecting against a defect along the electrical line.Type: ApplicationFiled: June 4, 2018Publication date: June 27, 2019Applicant: MEDIATEK Singapore Pte. Ltd.Inventors: Henry Arnold Park, Tamer Mohammed Ali, Shih-Hao Huang, Chien-Hua Wu