Abstract: A feedback controlled substrate bias generator having a substrate bias level sensing circuit, a charge pump circuit and an improved oscillator is disclosed. The substrate bias level sensing circuit is coupled to a semiconductor substrate for sensing a bias voltage of the semiconductor substrate and outputting a control signal in response to the sensed bias voltage. The charge pump circuit is coupled to the semiconductor substrate and the substrate bias level sensing circuit for receiving a clock pulse and the control signal and supplying the bias voltage to the semiconductor substrate in response to the received signals. The improved oscillator is coupled to the charge pump circuit for generating the clock pulse. The improved oscillator has a loop circuit having a plurality of serially and circularly coupled inverters each of which has a source terminal applied to voltage from a voltage source, an input terminal for receiving an input signal and an output terminal for outputting an output signal.

Abstract: A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.

Abstract: A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.

Abstract: A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.

Abstract: A PMOS 21 and an NMOS 22, which are connected in series between a power supply potential Vcc and a ground potential Vss, perform ON and Off operation in accordance with data signals G1 and G2 from an output buffer control circuit 40, and generate an output signal. A Vpp generating circuit 50 generates a potential Vpp higher than the power supply potential Vcc and a back gate bias of the PMOS 21 is set at the potential Vpp. Even if a latch-up trigger current due to a surge voltage is produced, the back gate bias of the PMOS 21 is set at Vpp and therefore a potential difference caused in an N type well resistor becomes small and a base potential of a parasitic bipolar transistor disposed between the N type well 2 and a substrate 1 becomes approximate to the potential Vpp. Accordingly, the current which flows into the substrate 1 is suppressed and a latch-up tolerance is improved.

Abstract: A semiconductor memory has a sense amplifier array shared by first and second memory cell arrays, which are selected by first and second selection signals. Interconnections between the sense amplifier array and the first memory cell array are controlled by a first transfer gate signal. When the first selection signal is inactive, the second selection signal is coupled through a first transfer gate driver to become the first transfer gate signal. When the first selection signal is active, the first transfer gate signal is decoupled from the second selection signal and driven to an elevated level.

Abstract: In semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells are connected is amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, the adverse effects due to the resistance of the power supply line is eliminated or reduced. This is achieved by coupling a power supply auxiliary line disposed within each memory cell array and a power supply main line disposed along the memory cell arrays by means of a resistive element having a resistance larger than the resistance of the power supply main line from the power supply to the memory cell array located farthest. Alternatively, the common node in each memory cell array is connected to said power supply main line via a resistive element and a sense amplifier drive transistor which is turned on and off by a control signal.

Abstract: A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First, to third memory cell blocks respectively have memory cell groups each including memory cells. First, to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal.

Abstract: A semiconductor memory has a sense amplifier array shared by first and second memory cell arrays, which are selected by first and second selection signals. Interconnections between the sense amplifier array and the first memory cell array are controlled by a first transfer gate signal. When the first selection signal is inactive, the second selection signal is coupled through a first transfer gate driver to become the first transfer gate signal. When the first selection signal is active, the first transfer gate signal is decoupled from the second selection signal and driven to an elevated level.

Abstract: In semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells are connected is amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, the adverse effects due to the resistance of the power supply line is eliminated or reduced. This is achieved by coupling a power supply auxiliary line disposed within each memory cell array and a power supply main line disposed along the memory cell arrays by means of a resistive element having a resistance larger than the resistance of the power supply main line from the power supply to the memory cell array located farthest. Alternatively, the common node in each memory cell array is connected to said power supply main line via a resistive element and a sense amplifier drive transistor which is turned on and off by a control signal.

Abstract: A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First to third memory cell blocks respectively have memory cell groups each including memory cells. First to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal.

Abstract: An integrated circuit semiconductor memory device includes a memory array having memory cells. A sensing circuit is coupled to the memory cells through one of first and second bit lines. A first conductive line is for applying a first voltage potential to the sensing circuit, and a second conductive line is for applying a second voltage potential to the sensing circuit. A first field effect transistor is provided having first, second electrodes connected to the first conductive line, and a gate electrode connected to the second conductive line. The sensing circuit has a second field effect transistor and a third field effect transistor of an opposite channel type to the second field effect transistor. The first, second and gate electrodes of the first field effect transistor are formed substantially simultaneously with the first, second and gate electrodes of one of the second and third field effect transistors during manufacture of the integrated circuit semiconductor memory device.

Abstract: A data bus clamping circuit for use in a semiconductor memory device includes a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, complementary data buses for transmitting data read out from the memory cell array, a data bus pull-up circuit for pulling up the complementary data buses, and a differential amplification type of readout circuit for amplifying on a differential basis data on the complementary data buses to output readout data.

Abstract: A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

Abstract: A data bus clamping circuit for use in a semiconductor memory device includes a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, complementary data buses for transmitting data read out from the memory cell array, a data bus pull-up circuit for pulling up the complementary data buses, and a differential amplification type of readout circuit for amplifying on a differential basis data on the complementary data buses to output readout data.

Abstract: A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

Abstract: A drive circuit for driving a semiconductor device includes a reference voltage level generator for outputting a reference voltage level which is associated with an input voltage level from an external power source. Supplied with the reference level, a ring oscillator oscillates a frequency signal having a predetermined frequency. A drive voltage level generator responds to the reference level and the frequency signal for producing a drive voltage level which is constantly substantially equal to the reference level in synchronism with the frequency signal. The drive voltage level generator feeds power from the external power source to the semiconductor device at the drive level, thereby driving the semiconductor load circuit.