Abstract: A redundancy decision circuit for specifying a redundant memory cell in a memory cell array when a normal cell is defective. The circuit includes a switching element, a fuse and a load circuit connected in series between high and low potential supplies. A switching driver drives the switching element. A hold circuit latches the potential at a node between the switching element and one of either the fuse and the load circuit. The circuit then generates a redundant decision signal.

Abstract: A redundancy decision circuit for specifying a redundant memory cell in a memory cell array when a normal cell is defective. The circuit includes a switching element, a fuse and a load circuit connected in series between high and low potential supplies. A switching driver drives the switching element. A hold circuit latches the potential at a node between the switching element and one of either the fuse and the load circuit. The circuit then generates a redundant decision signal.

Abstract: The present invention concerns a memory structure wherein a plurality of memory cells such as SRAM are provided in columns and a plurality of bit line pairs are provided for each column. A write circuit drives a first bit line pair and writes data to the memory cells in the column; at the same time, a sense amp reads data by means of the second bit line pair. In that case, the first bit line pair and second bit line pair, provided in the same column, are driven with opposite phase signals. To prevent the reversal of the small potential difference of the second bit line pair for reading at that time, two bit lines, one bit line from the first and second bit line pairs, are arranged parallel in a first wiring layer and are interspersed with a fixed potential wiring. Furthermore, the two other bit lines from the first and second bit line pairs, are arranged parallel in a second wiring layer provided via an insulating layer and are interspersed with a fixed potential wiring.

Abstract: According to the present invention, a synchronization circuit, which receives a plurality of input signals and a sync signal and performs a predetermined operation corresponding to said input signals in synchronization with said sync signal, comprising: a transition detector for detecting each transition of said plurality of input signals and for generating transition detection signal indicating that said transition occurs; and an internal sync signal generator for, upon the receipt of said sync signal, supplying an internal sync signal to said synchronization circuit when said detection signal indicate that said transition occurs, and for ceasing to supply said internal sync signal to said synchronization circuit, regardless of whether said sync signal is received, when said transition detection signal does not indicate that said transition occurs. According to the present invention, power consumption accompanying an unwanted, repeated operation can be eliminated.