Patents by Inventor Tamil Selvy Selvamuniandy

Tamil Selvy Selvamuniandy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741515
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 11, 2020
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20190287937
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 10373924
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 6, 2019
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20180247908
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: May 1, 2018
    Publication date: August 30, 2018
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 9966351
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 8, 2018
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20160365325
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: August 24, 2016
    Publication date: December 15, 2016
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 9449936
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: September 20, 2016
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20150179600
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 25, 2015
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20120135546
    Abstract: The present disclosure relates to the field of microelectronic substrate fabrication and, more particularly, to alignment inspection for vias formed in the microelectronic substrates. The alignment inspection may be achieved by determining the relative positions of fluorescing and non-fluorescing elements in a microelectronic substrate.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Inventors: Zhihua Zou, Liang William Zhang, Sheng Li, Tamil Selvy Selvamuniandy
  • Publication number: 20100301484
    Abstract: An LGA substrate includes a core (110), having build-up dielectric material (150), at least one metal layer (125), and solder resist (155) formed thereon, an electrically conductive land grid array pad (120) electrically connected to the metal layer, a nickel layer (121) on the electrically conductive land grid array pad, a palladium layer (122) on the nickel layer, and a gold layer (123) on the palladium layer.
    Type: Application
    Filed: July 15, 2010
    Publication date: December 2, 2010
    Inventors: Omar J. Bchir, Munehiro Toyama, Charan Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20090250824
    Abstract: A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center portion and a side portion that is tapered away relative to the center portion. In some embodiments, the bonding surface may comprise a round shape. In some embodiments, a gas escape path may be provided by the shape of the bonding surface to increase pin pull strength and/or solder strength. The package may further comprise a surface finish that may comprise a palladium layer with a reduced thickness to reduce the amount of palladium based IMC precipitation into the solder.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 8, 2009
    Inventors: Xiwang Qi, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy, Isao Yamada
  • Publication number: 20090166858
    Abstract: An LGA substrate includes a core (110), having build-up dielectric material (150), at least one metal layer (125), and solder resist (155) formed thereon, an electrically conductive land grid array pad (120) electrically connected to the metal layer, a nickel layer (121) on the electrically conductive land grid array pad, a palladium layer (122) on the nickel layer, and a gold layer (123) on the palladium layer.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Inventors: Omar J. Bchir, Munehiro Toyama, Charan Gurumurthy, Tamil Selvy Selvamuniandy